AMC131M01DFMR datasheet(33/81 Pages) TI

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8.4.3 Start-Up Behavior After a Pin Reset or RESET Command

Sending a RESET command or executing a pin reset using the SYNC/RESET pin disables the DC/DC converter

by resetting the DCDC_EN bit to 0b. Therefore, the start-up process following a RESET command or a pin reset

using the SYNC/RESET pin is similar to what occurs after power up. However, there is no tPOR_DVDD in the case

of a command or pin reset because the DVDD supply is already ramped.

Figure 8-15 shows the behavior after a pin reset using the SYNC/RESET pin. A reset is only generated if the

SYNC/RESET pin is held low longer than tw(RSL). If the pin is held low for a duration less then tw(RSL) but greater

than a CLKIN period, a synchronization occurs instead of a reset.

SYNC/RESET

Invalid data

Unsettled

filter data

Unsettled

filter data

Valid Sinc

filter data

tDATA

...

DRDY

CLKIN

SEC_FAIL

HLDO_OUT

90%

tPOR_SEC

...

SPI write to

configure

registers

Invalid data

tDATA

Figure 8-15. Start-Up Behavior After a Pin Reset and Settling Times

As shown in Figure 8-15, follow the same sequence for configuring the device and reading the SEC_FAIL bit in

the STATUS register as described in the Start-Up Behavior After Power-Up section to receive valid conversion

data after a RESET command or a pin reset using the SYNC/RESET pin.

8.4.4 Start-Up Behavior After a Pause in CLKIN

A pause in the clock signal provided at the CLKIN pin causes the power supply generated by the DC/DC

converter on the secondary (high) side to drop and can prevent the ADC circuit on the secondary side from

operating. The DC/DC converter is automatically re-enabled when the clock at the CLKIN pin resumes, and the

AMC131M01 registers do not need to be reconfigured. However, the supply voltage on the secondary (high) side

is not stable until the SEC_FAIL bit in the STATUS register is set to 0b.

Follow the same sequence for reading the SEC_FAIL bit in the STATUS register as described in the Start-Up

Behavior After Power-Up section to receive valid conversion data after the clock has been paused and re-started

at the CLKIN pin.

8.4.5 Synchronization

Synchronization can be performed by the host to make sure the ADC conversions are synchronized to an

external event. For example, synchronization can realign the data capture to the expected timing of the host if a

glitch on the clock causes the host and device to become out of synchronization.

The SYNC/RESET pin is a multifunction digital input pin that allows the host to synchronize conversions to an

external event or to reset the device. See the SYNC/RESET Pin section for more details regarding how the

device is reset.

Provide a negative pulse on the SYNC/RESET pin with a duration less than tw(RSL) but greater than a CLKIN

period to trigger synchronization. The device internally compares the leading negative edge of the SYNC/RESET

pulse to the internal clock that tracks the data rate. The internal data rate clock has timing equivalent to

the DRDY pin. If the negative edge on SYNC/RESET aligns with the internal data rate clock, the device is

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AMC131M01

SBASA57 – SEPTEMBER 2023

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