TMPR4955AF datasheet(151/168 Pages) TOSHIBA

151 / 168 page

Chapter 8 TX4955A Processor Interrupts

8-3

8.5

Asserting Interrupts

External writes to the CPU are directed to various internal resources, based on an internal

address map of the processor. An external write to any address writes to an architecturally

transparent register called the

Interrupt register; this register is available for external write

cycles, but not for external reads.

During a data cycle, SysAD (2

SysAD (2

SysAD (22222:16)

:16)

:16) are the write enables for the seven individual

Interrupt

SysAD (

SysAD (5555:0)

:0)

:0) are the values to be written into these bits. This allows any subset

of the

Interrupt register to be set or cleared with a single write request. Figure 8.4.1 shows the

mechanics of an external write to the

Interrupt register, along with the nonmaskable interrupt

described earlier.

Figure shows how the TX4955A hardware interrupts are readable through the

Cause

• Bits 4:0 of the Interrupt register are bit-wise ORed with the current value of the

interrupt pins Int

Int

Int*[4:0]

[4:0]

[4:0] and the result is directly readable as bits 14:10 of the

Cause

• Bit5 of the Interrupt register is ORed with the current value of the interrupt pin Int5*.

Bit15 of Cause register is selected this ORed signal or Timer Interrupt by TintDis.

IP (1:0) of the Cause register, which are described in Chapter 8 8.3, are software interrupts.

There is no hardware mechanism for setting or clearing the software interrupts.

Figure 8.5.1 shows the masking of the TX4955A interrupt signals.

• Cause register bits 15:8 (IP7-IP0) are AND-ORed with Status register interrupt mask

bits 15:8 (IM7-IM0) to mask individual interrupts.

• Status register bit 0 is a global Interrupt Enable (IE). It is ANDed with the output of the

AND-OR logic to produce the TX4955A interrupt signal. The

EXL bit in the Status

Figure 8.5.1 Masking of the TX4955A Interrupts

Status register

SR (0)

Status register

SR (15:8)

TX4955A Interrupt

Cause register

(15:8)

AND

function

AND-OR

function

IP7

IP6

IP5

IP4

IP3

IP2

IP1

IP0

IM4

IM3

IM2

IM1

IM0

IM5

IM6

IM7

External

interrupts

Software

interrupts

Timer interrupts

or Int5*

TMPR4955AF датащи(PDF) 151 Page - Toshiba Semiconductor

TMPR4955AF датащи(HTML) 151 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL