TMPR4955AF datasheet(118/168 Pages) TOSHIBA

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Chapter 6 TX4955A System Interface

6-46

Processor command

agent command

agent data

External

Processor address/data

812

611

SysAD

SCycle

SClock

SysCmd

EOK*

EReq*

PMaster*

Figure 6.3.14 Processor Request For Bus Arbitration And External Agent Release

Upon assertion of Reset

Reset

Reset* or ColdReset

ColdReset

ColdReset*, the processor becomes bus master and the

external agent must become slave.

This protocol guarantees that either the processor or an external agent is always bus

master. The master should never tristate the bus, except when giving up ownership of the

bus under the rules of the protocol.

6.3.7

Issuing Commands

When the processor is master of the bus and wishes to issue a command, it cannot

successfully issue the command until the external agent signals that it is ready to accept it.

This readiness is indicated by assertion of the EOK

EOK

EOK* signal. Being master, the processor

may place the command on the bus and continually reissue it while waiting for EOK

EOK

EOK* to be

asserted; however, the command is not considered issued until EOK

EOK

EOK* has been asserted for

two consecutive cycle (see the Timing Summary for EOK

EOK

EOK* earlier in this chapter).

If the EOK

EOK

EOK* signal is asserted in one cycle and then deasserted in the next, during which

time a command is issued, that command is considered killed and must be retried. When a

command is killed in this way, the processor begins to execute the read/write command.

This action must be ignored by the external agent. If a write command is killed, the data

cycle following this killed transaction must be ignored. If a read is killed, the processor

releases the bus one cycle after and (assuming no EReq

EReq

EReq*) regains mastership two cycles

later. This allows the processor to retry the transaction.

6.3.8

Processor Write Request

A processor write request is issued by the following:

•

driving a write command on the SysCmd bus

•

driving a write address on the SysAD bus

•

asserting PValid

PValid

PValid* for one cycle

•

driving the appropriate number of data identifiers on the SysCmd bus

•

driving data on the SysAD bus

•

asserting PValid

PValid

PValid*

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