TMPR4955AF datasheet(117/168 Pages) TOSHIBA

117 / 168 page

Chapter 6 TX4955A System Interface

6-45

6.3.6

Arbitration

The processor is the default master of the bus. It relinquishes ownership of the bus either

when an external agent requests and is granted the system interface, or until the processor

issues a read request. The transition from processor master to processor slave state is

arbitrated by the processor, using the System interface handshake signals EReq

EReq

EReq* and

PMaster

PMaster*.

When a processor read request is pending, the processor transitions to slave state by

deasserting PMaster

PMaster

PMaster*, allowing an external agent to return the read response data. The

processor remains in slave state until the external agent issues an

End Of Data read

response, whereupon the processor reassumes mastership, signalled by the assertion of

PMaster

PMaster*. Note that an external agent is able to retain mastership of the bus after an End

Of Data read response if the external agent arbitrates for mastership using EReq

EReq

EReq*.

When the processor is master, an external agent acquires control of the system interface

by asserting EReq

EReq

EReq*, and waiting for the processor to deassert PMaster

PMaster

PMaster*. The processor is

ready to enter slave state when it deasserts PMaster

PMaster

PMaster*. The external agent must go through

a three-step arbitration process (see the EReq

EReq

EReq* cycle in the Timing Summary) before

driving the bus. Once the external agent has become master through EReq

EReq

EReq* arbitration, it

can remain master as long as it continues to assert EReq

EReq

EReq*. The System interface returns to

master state (with the processor driving the bus) two cycles after EReq

EReq

EReq* is deasserted.

Figure 6.3.13 illustrates an arbitration for external requests.

External agent command

External agent data

812

611

SysAD

SCycle

SClock

SysCmd

EReq*

PMaster*

Figure 6.3.13 External Request Arbitration

When an external agent is master, it may always respond to a read with data. If the

external agent has become master by EReq

EReq

EReq*, it may issue transactions at will; that is, the

processor must always accept any command or data on the bus at any time. There is no

means for the processor to hold off the external agent once the external agent is master.

If the processor is in slave state and needs the bus,wait untile the external agent EReq*

deasserted. Thereafter, when the processor sees EReq

EReq

EReq* deasserted, it resumes bus

ownership, asserts the PMaster

PMaster

PMaster* line, and issues its own command. The processor becomes

master and drives the bus two cycles after EReq

EReq

EReq* is deasserted.

An illustration of a processor request for bus mastership and the release of the bus by the

external agent is illustrated in Figure 6.3.14.

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