IMX8MPCEC datasheet(9/111 Pages) NXP

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Modules list

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Modules list

The i.MX 8M Plus family of processors contains a variety of digital and analog modules. Table 4 describes

these modules in alphabetical order.

Table 4. i.MX 8M Plus modules list

Block mnemonic

Block name

Brief description

APBH-DMA

NAND Flash and BCH ECC

DMA Controller

DMA controller used for GPMI2 operation.

Arm

Arm Platform

The Arm Core Platform includes a quad Cortex-A53 core and a

Cortex-M7 core. The Cortex-A53 core includes associated

sub-blocks, such as the Level 2 Cache Controller, Snoop Control

Unit (SCU), General Interrupt Controller (GIC), private timers,

watchdog, and CoreSight debug modules. The Cortex-M7 core is

used as a customer microcontroller.

ASRC

Asynchronous Sample Rate

Converter

The Asynchronous Sample Rate Converter (ASRC) can process 4

groups of audio channels with an independent time-base

simultaneously. A group of channels with the same time-base (or

resampling ration) is referred to as a context. Each context has

independent processing pipelines. Contexts can be configured to

start and stop at any time without affecting the processing of other

contexts. The ASRC supports up to 32 audio channels, which can

either be assigned to a single context or spread across multiple

contexts.

BCH

Binary-BCH ECC Processor

The BCH module provides up to 62-bit ECC encoder/decoder for

NAND Flash controller (GPMI).

CAAM

Cryptographic accelerator and

assurance module

CAAM is a cryptographic accelerator and assurance module. CAAM

implements several encryption and hashing functions, a run-time

integrity checker, entropy source generator, and a Pseudo Random

Number Generator (PRNG). The PRNG is certifiable by the

Cryptographic Algorithm Validation Program (CAVP) of the National

Institute of Standards and Technology (NIST).

CAAM also implements a Secure Memory mechanism. In i.MX 8M

Plus processors, the secure memory provided is 32 KB.

CCM

GPC

SRC

Clock Control Module, General

Power Controller, System Reset

Controller

These modules are responsible for clock and reset distribution in the

system, and also for the system power management.

CSU

Central Security Unit

The Central Security Unit (CSU) is responsible for setting

comprehensive security policy within the i.MX 8M Plus platform.

CTI-0

CTI-1

CTI-2

CTI-3

CTI-4

Cross Trigger Interface

Cross Trigger Interface (CTI) allows cross-triggering based on inputs

from masters attached to CTIs. The CTI module is internal to the

Cortex-A53 core platform.

DAP

Debug Access Port

The DAP provides real-time access for the debugger without halting

the core to access:

• System memory and peripheral registers

• All debug configuration registers

The DAP also provides debugger access to JTAG scan chains.

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