IMX8MPCEC datasheet(70/111 Pages) NXP

70 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

For DDR Toggle mode, Figure 36 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid

window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI

samples NAND_DATA[7:0] at both the rising and falling edges of a delayed NAND_DQS signal, which

is provided by an internal DPLL. The delay value of this register can be controlled by the GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Plus

Applications Processor Reference Manual [IMX8MPRM]). Generally, the typical delay value is equal to

0x7, which means a 1/4 clock cycle delay is expected. But if the board delay is big enough and cannot be

ignored, the delay value should be made larger to compensate the board delay.

3.8.6

I2C bus characteristics

The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave. The I2C is

designed to be compatible with the I2C Bus Specification, version 2.1, by Philips Semiconductor (now

NXP Semiconductors).

3.8.7

CAN network AC electrical specifications

The Controller Area Network (CAN) module is a communication controller implementing the CAN

protocol according to the CAN with Flexible Data rate (CAN FD) protocol and the CAN 2.0B protocol

specification. The processor has two CAN modules available. Tx and Rx ports for both modules are

multiplexed with other I/O pins. See the IOMUXC chapter of the device reference manual to see which

pins expose Tx and Rx pins; these ports are named CAN_TX and CAN_RX, respectively.

3.8.8

HDMI Tx module parameters

The HDMI 2.0a Tx interface (controller and PHY) is complaint with following specifications:

NF24 postamble delay

tPOST

POST_DELAY

 T + 0.43 [see

note2]

—ns

NF28 Data write setup

tDS5

0.25

 tCK - 0.32

—

NF29 Data write hold

tDH5

0.25

 tCK - 0.79

—

NF30 NAND_DQS/NAND_DQ read setup skew

tDQSQ6

—3.18

NF31 NAND_DQS/NAND_DQ read hold skew

tQHS6

—3.27

AS minimum value can be 0, while DS/DH minimum value is 1.

2 T = tCK (GPMI clock period) - 0.075 ns (half of maximum p-p jitter).

3 CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started

with enough time of ALE/CLE assertion to low level.

4 PRE_DELAY + 1

 (AS + DS)

5 Shown in Figure 37.

6 Shown in Figure 38.

Table 52. Toggle mode timing parameters (continued)

Parameter

Symbol

Timing

T = GPMI Clock Cycle

Unit

Min.

Max.

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