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IMX8MPCEC датащи(PDF) 75 Page - NXP Semiconductors

номер детали IMX8MPCEC
подробное описание детали  i.MX 8M Plus Applications Processor Datasheet for Consumer Products
PDF  111 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

IMX8MPCEC датащи(HTML) 75 Page - NXP Semiconductors

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Electrical characteristics
i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021
NXP Semiconductors
75
Figure 42. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge and read strobe on the SCK rising edge. The FlexSPI controller
samples read data on a half-cycle delayed DQS falling edge.
3.8.12.1.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2
Table 59. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)
Symbol
Parameter
Min.
Max.
Unit
[D:] Frequency of operation
166
MHz
F5
[D:] Time from SCK to data valid
ns
F6
[D:] Time from SCK to DQS
ns
[D:] Time delta between TSCKD and
TSCKDQS
-2
2
ns
Table 60. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Symbol
Parameter
Min.
Max.
Unit
Notes
[D:] Frequency of operation
33
MHz
F1
[D:] Setup time for incoming data
8.67
ns
1
1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be
decreased by up to 2ns.
F2
[D:] Hold time for incoming data
0
ns
Table 61. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1, 0x2
Symbol
Parameter
Min.
Max.
Unit
Notes
[D:] Frequency of operation
66
MHz
F1
[D:] Setup time for incoming data
1.5
ns
1
1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be
decreased by up to 2ns.
F2
[D:] Hold time for incoming data
1
ns
F5
F6
F5
F6
F5
F6
FLEXSPI_SCLK
FLEXSPI_DATA[7:0]
FLEXSPI_DQS
Internal Sample Clock



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