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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX8MPCEC датащи(PDF) 53 Page - NXP Semiconductors |
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IMX8MPCEC датащи(HTML) 53 Page - NXP Semiconductors |
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53 / 111 page  Electrical characteristics i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021 NXP Semiconductors 53 3.8.3 Ethernet controller (ENET) AC electrical specifications Ethernet supports the following key features: • Support ENET AVB • Support IEEE 1588 • Support Energy Efficient Ethernet (EEE) • 1.8 V/3.3 V RMII operation, 1.8 V RGMII operation The following sections introduce the ENET AC electrical specifications. 3.8.3.1 ENET1 signal mapping The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. Table 44. ENET1 signal mapping (Sheet 1 of 2) Pad name Description Mode Alt mode Direction Comments GPIO1_IO00 ENET_PHY_REF_CLK_ROOT RGMII ALT1 O Reference clock for PHY. SAI1_RXFS enet1.1588_EVENT0_IN RMII/RGMII ALT4 I Capture/compare block input/output event bus signal. When configured for capture and a rising edge is detected, the current timer value is latched and transferred into the corresponding ENET_TCCRn register for inspection by software. When configured for compare, the corresponding signal 1588_EVENT is asserted for one cycle when the timer reaches the compare value programmed in register ENET_TCCRn. An interrupt or DMA request can be triggered if the corresponding bit in ENET_TCSRn[TIE] or ENET_TSCRn[TDRE] is set. SAI1_RXC enet1.1588_EVENT0_OUT RMII/RGMII ALT4 O — SAI1_RXD0 enet1.1588_EVENT1_IN RMII/RGMII ALT4 I — SAI1_RXD1 enet1.1588_EVENT1_OUT RMII/RGMII ALT4 O — SAI1_RXD2 enet1.MDC RMII/RGMII ALT4 O — SAI1_RXD3 enet1.MDIO RMII/RGMII ALT4 I/O — SAI1_RXD4 enet1.RGMII_RD0 RMII/RGMII ALT4 I — SAI1_RXD5 enet1.RGMII_RD1 RMII/RGMII ALT4 I — SAI1_RXD6 enet1.RGMII_RD2 RGMII ALT4 I Only used for RGMII SAI1_RXD7 enet1.RGMII_RD3 RGMII ALT4 I Only used for RGMII |
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