| поискавой системы для электроныых деталей |
|
IMX8MPCEC датащи(PDF) 79 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
IMX8MPCEC датащи(HTML) 79 Page - NXP Semiconductors |
|
79 / 111 page ![]() Electrical characteristics i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021 NXP Semiconductors 79 Figure 47. SAI timing—Master modes S6 SAI_BCLK to SAI_FS output invalid 0 — ns S7 SAI_BCLK to SAI_TXD valid — 2 ns S8 SAI_BCLK to SAI_TXD invalid 0 — ns S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 12 — ns S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 — ns Table 67. Slave mode SAI timing (50 MHz)1 1 TX does not support 50 MHz operation in Slave mode. Num Characteristic Min Max Unit S11 SAI_BCLK cycle time (input) 20 — ns S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period S13 SAI_FS input setup before SAI_BCLK 2 — ns S14 SAI_FA input hold after SAI_BCLK 2 — ns S17 SAI_RXD setup before SAI_BCLK 2 — ns S18 SAI_RXD hold after SAI_BCLK 2 — ns Table 68. Slave mode SAI timing (25 MHz) Num Characteristic Min Max Unit S11 SAI_BCLK cycle time (input) 40 — ns S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period Table 66. Master mode SAI timing (25 MHz) (continued) Num Characteristic Min Max Unit |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |