IMX8MPCEC datasheet(35/111 Pages) NXP

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Electrical characteristics

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Table 23 represents the timing parameters of the power-up sequence.

3.2.2

Power-down sequence

Figure 6 illustrates the power-down sequence of i.MX 8M Plus processor.

Figure 6. The power-down sequence

Table 23. Power-up sequence

Description

Min

Typ

Max

Unit

Delay from NVCC_SNVS_1P8 to stable 32K existed

—

Delay from PMIC_ON_REQ assert to VDD_SOC and analog 0.8 V on

—

Delay from VDD_SOC and analog 0.8 V assert to VDD_ARM on

——

Delay from VDD_ARM assert to analog 1.8 V on

——

Delay from analog 1.8 V assert to digital 1.8 V on

——

T10

Delay from digital 1.8 V assert to NVCC_DRAM on

——

T11

Delay from NVCC_DRAM assert to digital 2.5 V and 3.3 V on

——

T13

Delay from digital 2.5 V and 3.3 V assert to POR_B de-assert

—

tstep

Typical delay from POK1 of one supply to start of next supply

1 Power good at 85% of typical value

—

Uncertain period before PMIC_ON_REQ assert during NVCC_SNVS_1P8 ramp up.

For ramp up requirement, only VDD_ANA0_1P8 has 5

µs minimum requirement, others do not have such

requirement.

During power-up, make sure NVCC_xxx - PVCCx_1P8 < 2 V.

NVCC_xxx (2.5 and 3.3 V)

NVCC_DRAM

PVCCx_1P8, NVCC_xxx (1.8V)

VDD_ANAx_1P8, VDD_DRAM_PLL_1P8,VDD_MIPI_1P8

VDD_24M_XTAL_1P8,VDD_USB_1P8,VCC_PCI_1P8

VDD_ARM

VDD_SOC, VDD_ANA_0P8

VDD_PCI_0P8, VDD_USB_0P8

VDD_MIPI_0P8, VDD_DRAM_PLL_0P8

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