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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX8MPCEC датащи(PDF) 74 Page - NXP Semiconductors |
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IMX8MPCEC датащи(HTML) 74 Page - NXP Semiconductors |
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74 / 111 page  i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021 74 NXP Semiconductors Electrical characteristics Figure 40. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2 NOTE Timing shown is based on the memory generating read data on the SCK falling edge, and FlexSPI controller sampling read data on the falling edge. 3.8.12.1.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3 There are two cases when the memory provides both read data and the read strobe in SDR mode: •A1—Memory generates both read data and read strobe on SCK rising edge (or falling edge) •A2—Memory generates read data on SCK falling edge and generates read strobe on SCK rising edge Figure 41. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1) NOTE Timing shown is based on the memory generating read data and read strobe on the SCK rising edge. The FlexSPI controller samples read data on the DQS falling edge. Table 58. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1) Symbol Parameter Min. Max. Unit — [D:] Frequency of operation — 166 MHz F3 [D:] Time from SCK to data valid — — ns F4 [D:] Time from SCK to DQS — — ns — [D:] Time delta between TSCKD and TSCKDQS -2 2 ns F1 F2 F1 F2 FLEXSPI_SCLK FLEXSPI_DATA[7:0] Internal Sample Clock F3 F3 F4 F4 FLEXSPI_SCLK FLEXSPI_DATA[7:0] FLEXSPI_DQS |
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