IMX8MPCEC datasheet(45/111 Pages) NXP

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Electrical characteristics

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

and tolerances required to work with these memories are specified in the respective documents and are not

reprinted here.

Meeting the necessary timing requirements for a DDR memory system is highly dependent on the

components chosen and the design layout of the system as a whole. NXP cannot cover in this document

all the requirements needed to achieve a design that meets full system performance over temperature,

voltage, and part variation; PCB trace routing, PCB dielectric material, number of routing layers used,

placement of bulk/decoupling capacitors on critical power rails, VIA placement, GND and Supply planes

layout, and DDR controller/PHY register settings all are factors affecting the performance of the memory

system. Consult the hardware user guide for this device and NXP validated design layouts for information

on how to properly design a PCB for best DDR performance. NXP strongly recommends duplicating an

NXP validated design as much as possible in the design of critical power rails, placement of

bulk/decoupling capacitors and DDR trace routing between the processor and the selected DDR memory.

All supporting material is readily available on the device web page on

https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applicatio

ns-processors/i.mx-8-processors:IMX8-SERIES .

Processors that demonstrate full DDR performance on NXP validated designs, but do not function on

customer designs, are not considered marginal parts. A report detailing how the returned part behaved on

an NXP validated system will be provided to the customer as closure to a customer’s reported DDR issue.

Customers bear the responsibility of properly designing the Printed Circuit Board, correctly simulating and

modeling the designed DDR system, and validating the system under all expected operating conditions

(temperatures, voltages) prior to releasing their product to market.

3.7.3.1

Clock/data/command/address pin allocations

These processors uses generic names for clock, data, and command address bus (DCF—DRAM controller

functions); see Table 79 for details about mapping of clock, data, and command address signals of

LPDDR4 and DDR4 modes.

3.8

External peripheral interface parameters

The following subsections provide information on external peripheral interfaces.

Table 35. i.MX 8M Plus DRAM controller supported SDRAM configurations

Parameter

LPDDR4

DDR4

Number of Controllers

Number of Channels

N/A

Number of Chip Selects

Bus Width

32 bit

Maximum Clock Frequency

4000 MT/s

3200 MT/s

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