IMX8MPCEC datasheet(52/111 Pages) NXP

52 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

3.8.2.5

SDR50/SDR104 AC timing

Figure 19 depicts the timing of SDR50/SDR104, and Table 43 lists the SDR50/SDR104 timing

characteristics.

Figure 19. SDR50/SDR104 timing

3.8.2.6

Bus operation condition for 3.3 V and 1.8 V signaling

Signaling level of SD/eMMC4.5/5.0/5.1 can be 1.8 V or 3.3 V depending on the working mode. The DC

parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are identical to those shown in

Table 26, "GPIO DC parameters," on page 38.

Table 43. SDR50/SDR104 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

5—

SD2

Clock Low Time

tCL

0.46 x tCLK 0.54 x tCLK

SD3

Clock High Time

tCH

0.46 x tCLK 0.54 x tCLK

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4

uSDHC Output Delay

tOD

-3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

-1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD6

uSDHC Input Setup Time

tISU

2.4

—

SD7

uSDHC Input Hold Time

tIH

1.4

—

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1

1 Data window in SDR100 mode is variable.

SD8

uSDHC Output Data Window

tODW

0.5 x tCLK

—ns

SCK

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD8

SD7

SD6

SD4/SD5

SD2

SD3

SD1

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