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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX8MPCEC датащи(PDF) 78 Page - NXP Semiconductors |
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IMX8MPCEC датащи(HTML) 78 Page - NXP Semiconductors |
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78 / 111 page  i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021 78 NXP Semiconductors Electrical characteristics Figure 46. FlexSPI output timing in DDR mode 3.8.13 SAI/I2S switching specifications This section provides the AC timings for the SAI in Master (clocks driven) and Slave (clocks input) modes. All timings are given for non inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP] = 0) and non inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below. Table 65. Master mode SAI timing (50 MHz)1 1 To achieve 50 MHz for BCLK operation, clock must be set in feedback mode. Num Characteristic Min Max Unit S1 SAI_MCLK cycle time 20 — ns S2 SAI_MCLK pulse width high/low 40% 60% MCLK period S3 SAI_BCLK cycle time 20 — ns S4 SAI_BCLK pulse width high/low 40% 60% BCLK period S5 SAI_BCLK to SAI_FS output valid — 2 ns S6 SAI_BCLK to SAI_FS output invalid 0 — ns S7 SAI_BCLK to SAI_TXD valid — 2 ns S8 SAI_BCLK to SAI_TXD invalid 0 — ns S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 2 — ns S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 — ns Table 66. Master mode SAI timing (25 MHz) Num Characteristic Min Max Unit S1 SAI_MCLK cycle time 40 — ns S2 SAI_MCLK pulse width high/low 40% 60% MCLK period S3 SAI_BCLK cycle time 40 — ns S4 SAI_BCLK pulse width high/low 40% 60% BCLK period S5 SAI_BCLK to SAI_FS output valid — 2 ns TCSS TCK TDVO TDHO TDVO TDHO TCSH SCK CS SIO[0:7] |
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