IMX8MPCEC datasheet(58/111 Pages) NXP

58 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

GPIO1_IO08

enet_qos.1588_EVENT0_IN;

enet_qos.1588_EVENT0_AUX_IN

RMII/RGMII ALT1/ALT4

Capture/compare block

input/output event bus signal.

When configured for capture

and a rising edge is detected,

the current timer value is

latched and transferred into

the corresponding

ENET_TCCRn register for

inspection by software. When

configured for compare, the

corresponding signal

1588_EVENT is asserted for

one cycle when the timer

reaches the compare value

programmed in register

ENET_TCCRn. An interrupt

or DMA request can be

triggered if the corresponding

bit in ENET_TCSRn[TIE] or

ENET_TSCRn[TDRE] is set.

ALT1 is for

enet_qos.1588_EVENT1_IN.

ALT4 is for

enet_qos.1588_EVENT1_AU

X_IN.

GPIO1_IO09

enet_qos.1588_EVENT0_OUT

RMII/RGMII

ALT1

—

ENET_MDC

enet_qos.MDC

RMII/RGMII

ALT0

—

ENET_MDIO

enet_qos.MDIO

RMII/RGMII

ALT0

I/O

—

ENET_TD3

enet_qos.RGMII_TD3

RGMII

ALT0

Only used for RGMII

ENET_TD2

RMII.REF_CLK;

enet_qos.RGMII_TD2

RMII/RGMII ALT1/ALT0

I/O

ALT0 is only for RGMII TD2

output, ALT1 is for RMII clock.

Used as RMII clock and

RGMII data, there are two

RMII clock schemes:

• MAC generates output 50M

reference clock for PHY,

also MAC uses this 50M

clock.

• MAC uses external 50M

clock.

ENET_TD1

enet_qos.RGMII_TD1

RMII/RGMII

ALT0

—

ENET_TD0

enet_qos.RGMII_TD0

RMII/RGMII

ALT0

—

ENET_TX_CTL

RMII.TX_EN;

enet_qos.RGMII_TX_CTL

RMII/RGMII

ALT0

—

Table 47. ENET QOS signal mapping (continued)

Pad name

Description

Mode

Alt mode

Direction

Comments

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