CS47L35 datasheet(177/300 Pages) CIRRUS

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DS1085F3

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CS47L35

4.15 Interrupts

R6166 (0x1816)

IRQ1_Status_23

3 EVENT4_FULL_EINT1

Event Log 4 FIFO Full Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

2 EVENT3_FULL_EINT1

Event Log 3 FIFO Full Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 EVENT2_FULL_EINT1

Event Log 2 FIFO Full Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 EVENT1_FULL_EINT1

Event Log 1 FIFO Full Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6167 (0x1817)

IRQ1_Status_24

3 EVENT4_WMARK_EINT1

Event Log 4 FIFO Watermark Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

2 EVENT3_WMARK_EINT1

Event Log 3 FIFO Watermark Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 EVENT2_WMARK_EINT1

Event Log 2 FIFO Watermark Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 EVENT1_WMARK_EINT1

Event Log 1 FIFO Watermark Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6168 (0x1818)

IRQ1_Status_25

2 DSP3_DMA_EINT1

DSP3 DMA Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 DSP2_DMA_EINT1

DSP2 DMA Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 DSP1_DMA_EINT1

DSP1 DMA Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6170 (0x181A)

IRQ1_Status_27

2 DSP3_START1_EINT1

DSP3 Start 1 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 DSP2_START1_EINT1

DSP2 Start 1 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 DSP1_START1_EINT1

DSP1 Start 1 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6171 (0x181B)

IRQ1_Status_28

2 DSP3_START2_EINT1

DSP3 Start 2 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 DSP2_START2_EINT1

DSP2 Start 2 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 DSP1_START2_EINT1

DSP1 Start 2 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6173 (0x181D)

IRQ1_Status_30

2 DSP3_BUSY_EINT1

DSP3 Busy Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 DSP2_BUSY_EINT1

DSP2 Busy Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 DSP1_BUSY_EINT1

DSP1 Busy Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6174 (0x181E)

IRQ1_Status_31

0 MIF1_DONE_EINT1

MIF1 Done Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6175 (0x181F)

IRQ1_Status_32

0 MIF1_BLOCK_EINT1

MIF1 Block Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6208 (0x1840)

R6239 (0x185F)

IM_*

See

Footnote 1

For each x_EINT1 interrupt bit in R6144 to R6175, a

corresponding mask bit (IM_*) is provided in R6208 to R6239.

The mask bits are coded as follows:

0 = Do not mask interrupt

1 = Mask interrupt

R6272 (0x1880)

IRQ1_Raw_

Status_1

12 CTRLIF_ERR_STS1

Control Interface Error Status

0 = Normal

1 = Control Interface Error

7 BOOT_DONE_STS1

Boot Status

0 = Busy (boot sequence in progress)

1 = Idle (boot sequence completed)

Control register writes should not be attempted until Boot

Sequence has completed.

Table 4-89. Interrupt 1 Control Registers (Cont.)

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