CS47L35 datasheet(163/300 Pages) CIRRUS

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DS1085F3

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CS47L35

4.13 Low Power Sleep Configuration

The CS47L35 supports a low-power Sleep Mode, in which most functions are disabled and power consumption is

minimized. The CS47L35 enters Sleep Mode when the DCVDD supply is removed. Note that the AVDD and DBVDD1

supplies must be present throughout the Sleep Mode duration.

In Sleep Mode, the CS47L35 can generate an interrupt event in response to a change in voltage on the JACKDET1 or

JACKDET2 pins. This enables a jack insertion event (or other digital logic transition) to be used to trigger a wake-up of the

CS47L35.

The system clocks (SYSCLK, DSPCLK) should be disabled before selecting Sleep Mode. The external clock input

(MCLKn) may also be stopped, if desired.

The functionality and control fields associated with Sleep Mode are supported via an internal always-on supply domain.

The always-on control registers are listed in Table 4-81. These fields are maintained (i.e., not reset) in Sleep Mode.

Note that the control interface is not supported in Sleep Mode; read/write access to the always-on registers is not possible.

Access to the register map using any of the control interfaces should be ceased before selecting Sleep Mode.

The always-on digital I/O pins are listed in Table 4-82. All other digital input pins have no effect in Sleep Mode; all other

digital output pins are undriven (floating).

The IRQ output is normally deasserted in Sleep Mode. In Sleep Mode, the IRQ output can be asserted only in response

to the JACKDET1 or JACKDET2 inputs. If the IRQ output is asserted in Sleep Mode, it can be deasserted only after a

wake-up transition.

Output drivers and bus keepers are disabled in Sleep Mode, for all pins not on the always-on domain; this means that the

logic level on these pins is undefined. If a defined logic state is required during Sleep Mode (e.g., as input to another

device), an external pull resistor may be required. If an external pull resistor is connected to a pin that also supports a bus

keeper function, the pull resistance should be chosen carefully, taking into account the resistance of the bus keeper. See

Section 4.14.1 for specific notes concerning the GPIO pins.

Table 4-81. Sleep Mode Always-On Control Registers

Label

Reference

R710 (0x02C6)

MICD_CLAMP_OVD

See Section 4.12

MICD_CLAMP_MODE[3:0]

R723 (0x02D3)

JD2_ENA

JD1_ENA

R6150 (0x1806)

MICD_CLAMP_FALL_EINT1

See Section 4.15

MICD_CLAMP_RISE_EINT1

JD2_FALL_EINT1

JD2_RISE_EINT1

JD1_FALL_EINT1

JD1_RISE_EINT1

R6214 (0x1846)

IM_MICD_CLAMP_FALL_EINT1

IM_MICD_CLAMP_RISE_EINT1

IM_JD2_FALL_EINT1

IM_JD2_RISE_EINT1

IM_JD1_FALL_EINT1

IM_JD1_RISE_EINT1

R6784 (0x1A80)

IM_IRQ1

IRQ_POL

IRQ_OP_CFG

R6864 (0x1AD0)

RESET_PU

See Section 4.23

RESET_PD

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