CS47L35 datasheet(120/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.7 Digital Audio Interface Control

The AIF2 BCLK/LRCLK control fields are described in Table 4-42.

The AIF3 BCLK/LRCLK control fields are described in Table 4-43.

4.7.6

AIF Digital Audio Data Control

The fields controlling the audio data format, word length, and slot configurations for AIF1, AIF2, and AIF3 are described

in Table 4-44, Table 4-45, and Table 4-46 respectively.

Note that left-justified and DSP-B modes are valid in Master Mode only (i.e., BCLK and LRCLK are outputs from the

CS47L35).

The AIFn slot length is the number of BCLK cycles in one time slot within the overall LRCLK frame. The word length is the

number of valid data bits within each time slot. If the word length is less than the slot length, there are unused BCLK cycles

at the end of each time slot. The AIFn word length and slot length is independently selectable for the input (RX) and output

(TX) paths.

For each AIF input (RX) and AIF output (TX) channel, the position of the audio data sample within the LRCLK frame is

configurable. The x_SLOT fields define the time-slot position of the audio sample for the associated audio channel. Valid

selections are Slot 0 upwards. The time slots are numbered as shown in Fig. 4-41 through Fig. 4-44.

Note that, in DSP modes, the time slots are ordered consecutively from the start of the LRCLK frame. In I2S and

left-justified modes, the even-numbered time slots are arranged in the first half of the LRCLK frame, and the odd-numbered

time slots are arranged in the second half of the frame.

Table 4-42. AIF2 BCLK and LRCLK Control

Address

Bit

Label

Default

Description

R1344

(0x0540)

AIF2_

BCLK_Ctrl

4:0 AIF2_BCLK_

FREQ[4:0]

0x0C AIF2BCLK Rate. The AIF2BCLK rate must be less than or equal to SYSCLK/2.

0x00–0x01 = Reserved

0x02 = 64 kHz (58.8 kHz)

0x03 = 96 kHz (88.2 kHz)

0x04 = 128 kHz (117.6 kHz)

0x05 = 192 kHz (176.4 kHz)

0x06 = 256 kHz (235.2 kHz)

0x07 = 384 kHz (352.8 kHz)

0x08 = 512 kHz (470.4 kHz)

0x09 = 768 kHz (705.6 kHz)

0x0A = 1.024 MHz (940.8 kHz)

0x0B = 1.536 MHz (1.4112 MHz)

0x0C = 2.048 MHz (1.8816 MHz)

0x0D = 3.072 MHz (2.8824 MHz)

0x0E = 4.096 MHz (3.7632 MHz)

0x0F = 6.144 MHz (5.6448 MHz)

0x10 = 8.192 MHz (7.5264 MHz)

0x11 = 12.288 MHz (11.2896 MHz)

0x12 = 24.576 MHz (22.5792 MHz)

The frequencies in brackets apply for 44.1 kHz–related sample rates only (SAMPLE_RATE_

=01XXX).

R1350

(0x0546)

AIF2_Rx_

BCLK_Rate

12:0 AIF2_

BCPF[12:0]

0x0040 AIF2LRCLK Rate. Selects the number of BCLK cycles per AIF2LRCLK frame. AIF2LRCLK

clock = AIF2BCLK/AIF2_BCPF.

Integer (LSB = 1), Valid from 8 to 8191.

Table 4-43. AIF3 BCLK and LRCLK Control

Address

Bit

Label

Default

Description

R1408

(0x0580)

AIF3_

BCLK_Ctrl

4:0 AIF3_

BCLK_

FREQ[4:0]

0x0C AIF3BCLK Rate. The AIF3BCLK rate must be less than or equal to SYSCLK/2.

0x00–0x01 = Reserved

0x02 = 64 kHz (58.8 kHz)

0x03 = 96 kHz (88.2 kHz)

0x04 = 128 kHz (117.6 kHz)

0x05 = 192 kHz (176.4 kHz)

0x06 = 256 kHz (235.2 kHz)

0x07 = 384 kHz (352.8 kHz)

0x08 = 512 kHz (470.4 kHz)

0x09 = 768 kHz (705.6 kHz)

0x0A = 1.024 MHz (940.8 kHz)

0x0B = 1.536 MHz (1.4112 MHz)

0x0C = 2.048 MHz (1.8816 MHz)

0x0D = 3.072 MHz (2.8824 MHz)

0x0E = 4.096 MHz (3.7632 MHz)

0x0F = 6.144 MHz (5.6448 MHz)

0x10 = 8.192 MHz (7.5264 MHz)

0x11 = 12.288 MHz (11.2896 MHz)

0x12 = 24.576 MHz (22.5792 MHz)

The frequencies in brackets apply for 44.1 kHz–related sample rates only (SAMPLE_RATE_

= 01XXX).

R1414

(0x0586)

AIF3_Rx_

BCLK_Rate

12:0 AIF3_

BCPF[12:0]

0x0040 AIF3LRCLK Rate. Selects the number of BCLK cycles per AIF3LRCLK frame. AIF3LRCLK clock =

AIF3BCLK/AIF3_BCPF.

Integer (LSB = 1), Valid from 8 to 8191.

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