CS47L35 datasheet(117/300 Pages) CIRRUS

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DS1085F3

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CS47L35

4.7 Digital Audio Interface Control

4.7.3.1 LRCLK Advance

The timing of the AIFnLRCLK signal can be adjusted using AIFn_LRCLK_ADV. If this bit is set, the LRCLK signal transition

is advanced to the previous BCLK phase (as compared with the default behavior).

The LRCLK-advance option (AIFn_LRCLK_ADV = 1) is valid for DSP-A mode only, operating in Master Mode.

Note: BCLK inversion must be enabled (AIFn_BCLK_INV = 1) if the LRCLK-advance option is enabled.

The adjusted interface timing (AIFn_LRCLK_ADV = 1), is shown in Fig. 4-48. The left-channel MSB is available on the

second rising edge of BCLK, 1.5 BCLK cycles after the LRCLK rising edge—assuming the BCLK output is inverted.

Figure 4-48. LRCLK advance—DSP-A Master Mode

4.7.4

AIF Signal Path Enable

The AIF1 interface supports up to six input (RX) channels and up to six output (TX) channels. Each channel is enabled or

disabled using the bits defined in Table 4-38.

The AIF2 and AIF3 interfaces support up to two input (RX) channels and up to two output (TX) channels. Each channel is

enabled or disabled using the bits defined in Table 4-39 and Table 4-40.

The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The AIF signal paths

should be kept disabled (AIFn_TXm_ENA = 0, AIFn_RXm_ENA = 0) if SYSCLK is not enabled. See Section 4.16 for

details of the system clocks (including requirements for reconfiguring SYSCLK while audio paths are enabled).

The audio interfaces can be reconfigured if enabled, including changes to the LRCLK frame length and the channel

time-slot configurations. Care is required to ensure that this on-the-fly reconfiguration does not cause corruption to the

active signal paths. Wherever possible, it is recommended to disable all channels before changing the AIF configuration.

The CS47L35 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the

commanded signal paths and processing functions. If the frequency is too low, an attempt to enable an AIF signal path

fails. Note that active signal paths are not affected under such circumstances.

R1410 (0x0582)

AIF3_Rx_Pin_Ctrl

3AIF3_

LRCLK_ADV

AIF3 Audio Interface LRCLK Advance

0 = Normal

1 = AIF3LRCLK transition is advanced to the previous BCLK phase

2AIF3_

LRCLK_INV

AIF3 Audio Interface LRCLK Invert

0 = AIF3LRCLK not inverted

1 = AIF3LRCLK inverted

1AIF3_

LRCLK_FRC

AIF3 Audio Interface LRCLK Output Control

0 = Normal

1 = AIF3LRCLK always enabled in Master Mode

0AIF3_

LRCLK_

MSTR

AIF3 Audio Interface LRCLK Master Select

0 = AIF3LRCLK Slave Mode

1 = AIF3LRCLK Master Mode

Table 4-37. AIF3 Master/Slave Control (Cont.)

Label

Default

Description

n-1

n-2

n-1

n-2

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

Input Word Length (WL)

1/Fs

LRCLK

BCLK

RXDAT/

TXDAT

1.5 BCLK

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