CS47L35 datasheet(122/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.7 Digital Audio Interface Control

The AIF3 data control fields are described in Table 4-46.

4.7.7

AIF TDM and Tristate Control

The AIFn output pins are tristated when the AIFn_TRI bit is set. Note that this function only affects output pins configured

for the respective AIFn function—a GPIO pin that is configured for a different function is not affected by AIFn_TRI. See

Section 4.14 to configure the GPIO pins.

Under default conditions, the AIFnTXDAT output is held at Logic 0 when the CS47L35 is not transmitting data (i.e., during

time slots that are not enabled for output by the CS47L35). If the AIFnTX_DAT_TRI bit is set, the CS47L35 tristates the

respective AIFnTXDAT pin when not transmitting data, allowing other devices to drive the AIFnTXDAT connection.

R1354 (0x054A)

AIF2_Frame_Ctrl_

5:0 AIF2TX2_

SLOT[5:0]

0x1

AIF2 TX Channel 2 Slot position

Defines the TX time slot position of the Channel 2 audio sample

Integer (LSB=1); Valid from 0 to 63

R1361 (0x0551)

AIF2_Frame_Ctrl_

5:0 AIF2RX1_

SLOT[5:0]

0x0

AIF2 RX Channel 1 Slot position

Defines the RX time slot position of the Channel 1 audio sample

Integer (LSB=1); Valid from 0 to 63

R1362 (0x0552)

AIF2_Frame_Ctrl_

5:0 AIF2RX2_

SLOT[5:0]

0x1

AIF2 RX Channel 2 Slot position

Defines the RX time slot position of the Channel 2 audio sample

Integer (LSB=1); Valid from 0 to 63

Table 4-46. AIF3 Digital Audio Data Control

Label

Default

Description

R1412 (0x0584)

AIF3_Format

2:0 AIF3_FMT[2:0]

000

AIF3 Audio Interface Format

000 = DSP Mode A

001 = DSP Mode B

010 = I2S mode

011 = Left-Justified mode

Other codes are reserved.

R1415 (0x0587)

AIF3_Frame_Ctrl_

13:8 AIF3TX_WL[5:0]

0x18 AIF3 TX Word Length (Number of valid data bits per slot)

Integer (LSB = 1); Valid from 16 to 32

7:0 AIF3TX_SLOT_

LEN[7:0]

0x18 AIF3 TX Slot Length (Number of BCLK cycles per slot)

Integer (LSB = 1); Valid from 16 to 128

R1416 (0x0588)

AIF3_Frame_Ctrl_

13:8 AIF3RX_WL[5:0]

0x18 AIF3 RX Word Length (Number of valid data bits per slot)

Integer (LSB = 1); Valid from 16 to 32

7:0 AIF3RX_SLOT_

LEN[7:0]

0x18 AIF3 RX Slot Length (Number of BCLK cycles per slot)

Integer (LSB = 1); Valid from 16 to 128

R1417 (0x0589)

AIF3_Frame_Ctrl_

5:0 AIF3TX1_

SLOT[5:0]

0x0

AIF3 TX Channel 1 Slot position

Defines the TX time slot position of the Channel 1 audio sample

Integer (LSB=1); Valid from 0 to 63

R1418 (0x058A)

AIF3_Frame_Ctrl_

5:0 AIF3TX2_

SLOT[5:0]

0x1

AIF3 TX Channel 2 Slot position

Defines the TX time slot position of the Channel 2 audio sample

Integer (LSB=1); Valid from 0 to 63

R1425 (0x0591)

AIF3_Frame_Ctrl_

5:0 AIF3RX1_

SLOT[5:0]

0x0

AIF3 RX Channel 1 Slot position

Defines the RX time slot position of the Channel 1 audio sample

Integer (LSB=1); Valid from 0 to 63

R1426 (0x0592)

AIF3_Frame_Ctrl_

5:0 AIF3RX2_

SLOT[5:0]

0x1

AIF3 RX Channel 2 Slot position

Defines the RX time slot position of the Channel 2 audio sample

Integer (LSB=1); Valid from 0 to 63

Table 4-45. AIF2 Digital Audio Data Control (Cont.)

Label

Default

Description

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