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CS47L35 датащи(PDF) 116 Page - Cirrus Logic |
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CS47L35 датащи(HTML) 116 Page - Cirrus Logic |
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116 / 300 page ![]() 116 DS1085F3 CS47L35 4.7 Digital Audio Interface Control The AIF2 master/slave control registers are described in Table 4-36. The AIF3 master/slave control registers are described in Table 4-37. R1282 (0x0502) AIF1_Rx_Pin_Ctrl 3AIF1_ LRCLK_ ADV 0 AIF1 Audio Interface LRCLK Advance 0 = Normal 1 = AIF1LRCLK transition is advanced to the previous BCLK phase 2AIF1_ LRCLK_INV 0 AIF1 Audio Interface LRCLK Invert 0 = AIF1LRCLK not inverted 1 = AIF1LRCLK inverted 1AIF1_ LRCLK_ FRC 0 AIF1 Audio Interface LRCLK Output Control 0 = Normal 1 = AIF1LRCLK always enabled in Master Mode 0AIF1_ LRCLK_ MSTR 0 AIF1 Audio Interface LRCLK Master Select 0 = AIF1LRCLK Slave Mode 1 = AIF1LRCLK Master Mode Table 4-36. AIF2 Master/Slave Control Register Address Bit Label Default Description R1344 (0x0540) AIF2_BCLK_Ctrl 7AIF2_BCLK_ INV 0 AIF2 Audio Interface BCLK Invert 0 = AIF2BCLK not inverted 1 = AIF2BCLK inverted 6AIF2_BCLK_ FRC 0 AIF2 Audio Interface BCLK Output Control 0 = Normal 1 = AIF2BCLK always enabled in Master Mode 5AIF2_BCLK_ MSTR 0 AIF2 Audio Interface BCLK Master Select 0 = AIF2BCLK Slave Mode 1 = AIF2BCLK Master Mode R1346 (0x0542) AIF2_Rx_Pin_Ctrl 3AIF2_ LRCLK_ADV 0 AIF2 Audio Interface LRCLK Advance 0 = Normal 1 = AIF2LRCLK transition is advanced to the previous BCLK phase 2AIF2_ LRCLK_INV 0 AIF2 Audio Interface LRCLK Invert 0 = AIF2LRCLK not inverted 1 = AIF2LRCLK inverted 1AIF2_ LRCLK_FRC 0 AIF2 Audio Interface LRCLK Output Control 0 = Normal 1 = AIF2LRCLK always enabled in Master Mode 0AIF2_ LRCLK_ MSTR 0 AIF2 Audio Interface LRCLK Master Select 0 = AIF2LRCLK Slave Mode 1 = AIF2LRCLK Master Mode Table 4-37. AIF3 Master/Slave Control Register Address Bit Label Default Description R1408 (0x0580) AIF3_BCLK_Ctrl 7AIF3_BCLK_ INV 0 AIF3 Audio Interface BCLK Invert 0 = AIF3BCLK not inverted 1 = AIF3BCLK inverted 6AIF3_BCLK_ FRC 0 AIF3 Audio Interface BCLK Output Control 0 = Normal 1 = AIF3BCLK always enabled in Master Mode 5AIF3_BCLK_ MSTR 0 AIF3 Audio Interface BCLK Master Select 0 = AIF3BCLK Slave Mode 1 = AIF3BCLK Master Mode Table 4-35. AIF1 Master/Slave Control (Cont.) Register Address Bit Label Default Description |
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