CS47L35 datasheet(107/300 Pages) CIRRUS

107 / 300 page

DS1085F3

107

CS47L35

4.6 Digital Audio Interface

The CS47L35 provides three audio interfaces, AIF1, AIF2, and AIF3. Each of these is independently configurable on the

respective transmit (TX) and receive (RX) paths. AIF1 supports up to six channels of input and output signal paths; AIF2

and AIF3 support up to two channels of input and output signal paths.

The data sources for the audio interface transmit (TX) paths can be selected from any of the CS47L35 input signal paths,

or from the digital-core processing functions. The audio interface receive (RX) paths can be selected as inputs to any of

the digital-core processing functions or digital-core outputs. See Section 4.3 for details of the digital-core routing options.

The digital audio interfaces provide flexible connectivity for multiple processors and other audio devices. Typical

connections include applications processor, baseband processor, and wireless transceiver. Note that the SLIMbus

interface also provides digital audio input/output paths, providing options for additional interfaces. A typical configuration

is shown in Fig. 4-34.

The audio interface AIF1 is referenced to DBVDD1; interfaces AIF2 and AIF3 are referenced to DBVDD2. This enables

the CS47L35 to connect easily between application subsystems on different voltage domains.

R315440 (0x4_D030)

DSPGP_SET1_Level_1

R315472 (0x4_D050)

DSPGP_SET2_Level_1

R315504 (0x4_D070)

DSPGP_SET3_Level_1

R315536 (0x4_D090)

DSPGP_SET4_Level_1

15 DSPGP16_SETn_LVL

DSP SETn GPIO16 Output Level

0 = Logic 0

1 = Logic 1

14 DSPGP15_SETn_LVL

DSP SETn GPIO15 Output Level

13 DSPGP14_SETn_LVL

DSP SETn GPIO14 Output Level

12 DSPGP13_SETn_LVL

DSP SETn GPIO13 Output Level

11 DSPGP12_SETn_LVL

DSP SETn GPIO12 Output Level

10 DSPGP11_SETn_LVL

DSP SETn GPIO11 Output Level

9 DSPGP10_SETn_LVL

DSP SETn GPIO10 Output Level

8 DSPGP9_SETn_LVL

DSP SETn GPIO9 Output Level

7 DSPGP8_SETn_LVL

DSP SETn GPIO8 Output Level

6 DSPGP7_SETn_LVL

DSP SETn GPIO7 Output Level

5 DSPGP6_SETn_LVL

DSP SETn GPIO6 Output Level

4 DSPGP5_SETn_LVL

DSP SETn GPIO5 Output Level

3 DSPGP4_SETn_LVL

DSP SETn GPIO4 Output Level

2 DSPGP3_SETn_LVL

DSP SETn GPIO3 Output Level

1 DSPGP2_SETn_LVL

DSP SETn GPIO2 Output Level

0 DSPGP1_SETn_LVL

DSP SETn GPIO1 Output Level

Table 4-34. DSP GPIO Control (Cont.)

Bit

Label

Default

Description

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