CS47L35 datasheet(104/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.5 DSP Peripheral Control

4.5.4

DSP GPIO

The DSP GPIO function provides an advanced I/O capability, supporting the requirements of the CS47L35 as a

multipurpose sensor hub.

4.5.4.1 Overview

The CS47L35 supports up to 16 GPIO pins; these are implemented as alternate functions to a pin-specific capability.

The GPIOs can be used to provide status outputs and control signals to external hardware; the supported functions include

interrupt output, FLL clock output, accessory detection status, and S/PDIF or PWM-coded audio channels; see

Section 4.14.

The GPIOs can support miscellaneous logic input and output, interfacing directly with the integrated DSPs, or with the Host

Application software. A basic level of I/O functionality is described in Section 4.14, under the configuration where GPn_

FN = 0x001. The GPn_FN field selects the functionality for the respective pin, GPIOn.

The DSP GPIO pins are accessed using maskable sets of I/O control registers; this allows the selected combinations of

GPIOs to be controlled with ease, regardless of how the allocation of GPIO pins has been implemented in hardware. In a

typical use case, one GPIO mask is defined for each DSP, or for each functional process; this provides a highly efficient

mechanism for each DSP to independently access the respective input and output signals.

4.5.4.2 DSP GPIO Control

The DSP GPIO function is selected by setting GPn_FN = 0x002 for the respective GPIO pin (where n identifies the

applicable GPIOn pin).

Each DSP GPIO is controlled using bits that determine the direction (input/output) and the logic state (0/1) of the pin. These

bits are replicated in four control sets; each which can determine the logic level of any DSP GPIO.

Mask bits are provided within each control set, to determine which of the control sets has control of each DSP GPIO. To

avoid logic contention, a DSP GPIO output must be controlled (unmasked) in a maximum of one control set at any time.

Note that write access to the direction control bits (DSPGPn_SETx_DIR) and level control bits (DSPGPn_SETx_LVL) is

only valid when the channel (DSPGPn) is unmasked in the respective control set. Writes to these fields are implemented

for the unmasked DSP GPIOs, and are ignored in respect of the masked DSP GPIOs. Note that the level control bits

(DSPGPn_SETx_LVL) provide output level control only—they cannot be used to read the status of DSP GPIO inputs.

The logic level of the unmasked DSP GPIO outputs in any control set can be configured using a single register write.

Writing to the output level control registers determines the logic level of the unmasked DSP GPIOs in that set only; all other

outputs are unaffected.

DSP GPIO status bits are provided, indicating the logic level of every input or output pin that is configured as a DSP GPIO.

The DSPGPn_STS bits also provide logic-level indication for any pin that is configured as a GPIO input, with GPn_

FN = 0x001.Note that there is only one set of DSP GPIO status bits.

The status bits indicate the logic level of the DSP GPIO outputs. The respective pins are driven as outputs if configured

as a DSP GPIO output, and unmasked in one of the control sets. Note that a DSP GPIO continues to be driven as an

output, even if the mask bit is subsequently asserted in that set. The pin only ceases to be driven if it is configured as a

DSP GPIO input and is unmasked in one of the control sets, or if the pin is configured as an input under a different GPn_

FN field selection.

Base address

+0x08

Timern_Status

0TIMERn_

RUNNING_STS

Timer Running Status

0 = Timer stopped

1 = Timer running

Base address

+0x0A

Timern_Count_

Readback

31:0 TIMERn_CUR_

COUNT[31:0]

0x0000 Timer Current Count value

Table 4-33. General-Purpose Timer (TIMERn) Control (Cont.)

Bit

Label

Default

Description

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