CS47L35 datasheet(103/300 Pages) CIRRUS

103 / 300 page

DS1085F3

103

CS47L35

4.5 DSP Peripheral Control

Table 4-33. General-Purpose Timer (TIMERn) Control

Bit

Label

Default

Description

Timer 1 Base Address = R311296 (0x4_C000)

Timer 2 Base Address = R311424 (0x4_C080)

Timer 3 Base Address = R311552 (0x4_C100)

Timer 4 Base Address = R311680 (0x4_C180)

Base address

Timern_Control

TIMERn_

CONTINUOUS

Timer Continuous Mode select

0 = Single mode

1 = Continuous mode

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field

TIMERn_DIR

Timer Count Direction

0 = Down

1 = Up

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field

18:16 TIMERn_

PRESCALE[2:0]

000

Timer Count Rate Prescale

000 = Divide by 1

001 = Divide by 2

010 = Divide by 4

011 = Divide by 8

100 = Divide by 16

101 = Divide by 32

110 = Divide by 64

111 = Divide by 128

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field

14:12 TIMERn_

REFCLK_

DIV[2:0]

000

Timer Reference Clock Divide

(Not valid for DSPCLK source).

000 = Divide by 1

001 = Divide by 2

010 = Divide by 4

011 = Divide by 8

100 = Divide by 16

101 = Divide by 32

110 = Divide by 64

111 = Divide by 128

If DSPCLK is enabled, and DSPCLK is not selected as source, the output frequency from

this divider must be set less than or equal to DSPCLK/3, and less than or equal to

12 MHz.

If DSPCLK is disabled, the output of this divider is used as clock reference for any

associated event logger. In this case, the divider output corresponds to the frequency of

event logging opportunities on the respective modules.

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field

10:8 TIMERn_

REFCLK_

FREQ_SEL[2:0]

000

Timer Reference Frequency Select

Only valid when SYSCLK or DSPCLK is the source. The selected frequency must be less

than or equal to the frequency of the respective source.

All other codes are reserved

Note that, because DSPCLK could be any frequency (within the valid ranges), it is not

possible to quote exact frequencies in this field definition. The exact frequency is derived

as DSPCLK divided by 1, 2, 4, 8, or 16.

Timer must be stopped (TIMERn_RUNNING_STS=0) when updating this field.

SYSCLK Source:

000 = 6.144 MHz (5.6448 MHz)

001 = 12.288 MHz (11.2896 MHz)

010 = 24.576 MHz (22.5792 MHz)

011 = 49.152 MHz (45.1584 MHz)

All other codes are reserved

DSPCLK Source:

000 = 5.5 MHz to 9.375 MHz

001 = 9.375 MHz to 18.75 MHz

010 = 18.75 MHz to 37.5 MHz

011 = 37.5 MHz to 75 MHz

3:0

TIMERn_

REFCLK_

SRC[3:0]

0000 Timer Reference Source Select. Timer must be stopped (TIMERn_RUNNING_STS=0)

when updating this field. Codes not listed are reserved.

0000 = DSPCLK

0001 = 32kHz clock

0100 = MCLK1

0101 = MCLK2

1000 = SYSCLK

1100 = GPIO2

1101 = GPIO9

1110 = GPIO13

1111 = GPIO16

Base address

+0x02

Timern_Count_

Preset

31:0 TIMERn_MAX_

COUNT[31:0]

0x0000

_0000

Timer Maximum Count

Final count value (when counting up)

Starting count value (when counting down)

Timer must be stopped (TIMERn_RUNNING_STS = 0) when updating this field

Base address

+0x06

Timern_Start_

and_Stop

4TIMERn_STOP

Timer Stop Control

Write 1 to stop.

0TIMERn_

START

Timer Start Control

Write 1 to start.

If the timer is already running, it restarts from its initial value.

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