CS47L35 datasheet(109/300 Pages) CIRRUS

109 / 300 page

DS1085F3

109

CS47L35

4.6 Digital Audio Interface

4.6.1

Master and Slave Mode Operation

The CS47L35 digital audio interfaces can operate as a master or slave, as shown in Fig. 4-35 and Fig. 4-36. The

associated control bits are described in Section 4.7.

4.6.2

Audio Data Formats

The CS47L35 digital audio interfaces can be configured to operate in I2S, left-justified, DSP-A, or DSP-B interface modes.

Note that left-justified and DSP-B modes are valid in Master Mode only (i.e., BCLK and LRCLK are outputs from the

CS47L35).

The digital audio interfaces also provide flexibility to support multiple slots of audio data within each LRCLK frame. This

flexibility allows multiple audio channels to be supported within a single LRCLK frame.

The data formats described in this section are generic descriptions, assuming only one stereo pair of audio samples per

LRCLK frame. In these cases, the AIF is configured to transmit (or receive) in the first available position in each frame (i.e.,

the Slot 0 position).

The options for multichannel operation are described in Section 4.6.3.

The audio data modes supported by the CS47L35 are described as follows. Note that the BCLK and LRCLK signals are

configurable—the polarity of these signals can be inverted if required, and the timing of the LRCLK transition can also be

adjusted. The following descriptions all assume the default configuration (noninverted polarity, normal timing) of these

signals.

• In DSP modes, the left channel MSB is available on either the first (Mode B) or second (Mode A) rising edge of

BCLK following a rising edge of LRCLK. Right-channel data immediately follows left channel data. Depending on

word length, BCLK frequency, and sample rate, there may be unused BCLK cycles between the LSB of the right

channel data and the next sample.

In Master Mode, the LRCLK output resembles the frame pulse shown in Fig. 4-37 and Fig. 4-38. In Slave Mode, it

is possible to use any length of frame pulse less than 1/Fs, providing the falling edge of the frame pulse occurs at

least one BCLK period before the rising edge of the next frame pulse.

PCM operation is supported in DSP interface mode. CS47L35 data that is output on the left channel is read as mono

data by the receiving equipment. Mono PCM data received by the CS47L35 is treated as left-channel data. This

may be routed to the left/right playback paths using the control fields described in Section 4.3.

Figure 4-35. Master Mode

Figure 4-36. Slave Mode

TXDAT

LRCLK

RXDAT

BCLK

Processor

CS47L35

TXDAT

LRCLK

RXDAT

BCLK

Processor

CS47L35

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