CS47L35 datasheet(111/300 Pages) CIRRUS

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DS1085F3

111

CS47L35

4.6 Digital Audio Interface

4.6.3

AIF Time-Slot Configuration

Digital audio interface AIF1 supports multichannel operation, with up to six channels of input and output in each case. A

high degree of flexibility is provided to define the position of the audio samples within each LRCLK frame; the audio

channel samples may be arranged in any order within the frame.

AIF2 and AIF3 also provide flexible configuration options, but these interfaces support only one stereo input and one

stereo output path.

Note that, on each interface, all input and output channels must operate at the same sample rate (Fs).

Each of the audio channels can be enabled or disabled independently on the transmit (TX) and receive (RX) signal paths.

For each enabled channel, the audio samples are assigned to one time slot within the LRCLK frame.

In DSP modes, the time slots are ordered consecutively from the start of the LRCLK frame. In I2S and left-justified modes,

the even-numbered time slots are arranged in the first half of the LRCLK frame, and the odd-numbered time slots are

arranged in the second half of the frame.

The time slots are assigned independently for the transmit (TX) and receive (RX) signal paths. There is no requirement to

assign every available time slot to an audio sample; slots may be left unused, if desired. Care is required, however, to

ensure that no time slot is allocated to more than one audio channel.

The number of BCLK cycles within a slot is configurable; this is the slot-length. The number of valid data bits within a slot

is also configurable; this is the word length. The number of BCLK cycles per LRCLK frame must be configured; it must be

ensured that there are enough BCLK cycles within each LRCLK frame to transmit or receive all of the enabled audio

channels.

Examples of the AIF time-slot configurations are shown in Fig. 4-41 through Fig. 4-44. One example is shown for each of

the four possible data formats.

Fig. 4-41 shows an example of DSP Mode A format. Four enabled audio channels are shown, allocated to time slots 0

through 3.

Figure 4-41. DSP Mode A Example

LRCLK

Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7

...

Slot 0

Slot 3

AIF1[TX1/RX1]_SLOT = 0

Channel 1

Channel 2

Channel 3

Channel 4

BCLK

TXDAT/

RXDAT

Slot 1

Slot 2

AIF1[TX2/RX2]_SLOT = 1

AIF1[TX3/RX3]_SLOT = 2

AIF1[TX4/RX4]_SLOT = 3

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