CS47L35 datasheet(101/300 Pages) CIRRUS

101 / 300 page

DS1085F3

101

CS47L35

4.5 DSP Peripheral Control

4.5.3

General-Purpose Timers

The CS47L35 incorporates four general-purpose timers, which support a wide variety of uses. In particular, these timers

provide essential support for the sensor-hub capability.

4.5.3.1 Overview

The timers allow time stamp information to be associated with external sensor activity, and other system events, enabling

real time data to be more easily integrated into user applications. The timers allow many advanced functions to be

implemented with a high degree of autonomy from a host processor.

The timers can use either internal system clocks, or external clock signals, as a reference. The selected reference is scaled

down, using configurable dividers, to the required clock count frequency.

4.5.3.2 Timer Control

The reference clock for each timer is selected using TIMERn_REFCLK_SRC, (where n identifies the applicable timer,

1–4).

If SYSCLK or DSPCLK is selected, a lower clock frequency, derived from the applicable system clock, can be selected

using the TIMERn_REFCLK_FREQ_SEL field. The applicable division ratio is determined automatically, assuming the

respective clock source has been correctly configured as described in Section 4.16.

If any source other than DSPCLK is selected, the clock can be further divided using TIMERn_REFCLK_DIV. Division ratios

in the range 1 to 128 can be selected.

Note that, if DSPCLK is enabled, the CS47L35 synchronizes the selected reference clock to DSPCLK. As a result of this,

if a non-DSPCLK is selected as source, the following additional constraints must be observed: the reference clock

frequency (after TIMERn_REFCLK_FREQ_SEL and after TIMERn_REFCLK_DIV) must be less than DSPCLK / 3, and

must be less than 12 MHz; it must also be close to 50% duty cycle. The TIMERn_REFCLK_DIV field can be used to ensure

that these criteria are met.

One final division, controlled by TIMERn_PRESCALE, determines the timer count frequency. This field is valid for all clock

reference sources; division ratios in the range 1 to 128 can be selected. The output from this division corresponds to the

frequency at which the TIMERn_COUNT fields are incremented (or decremented).

jd1_fall

226

spk_overheat_warn

369

event2_wmark

jd2_rise

256

gpio1

370

event3_wmark

jd2_fall

257

gpio2

371

event4_wmark

100

micd_clamp_rise

258

gpio3

384

dsp1_dma

101

micd_clamp_fall

259

gpio4

385

dsp2_dma

128

drc1_sig_det

260

gpio5

386

dsp3_dma

129

drc2_sig_det

261

gpio6

416

dsp1_start1

160

dsp_irq1

262

gpio7

417

dsp2_start1

161

dsp_irq2

263

gpio8

418

dsp3_start1

162

dsp_irq3

264

gpio9

432

dsp1_start2

163

dsp_irq4

265

gpio10

433

dsp2_start2

164

dsp_irq5

266

gpio11

434

dsp3_start2

165

dsp_irq6

267

gpio12

448

dsp1_start

166

dsp_irq7

268

gpio13

449

dsp2_start

167

dsp_irq8

269

gpio14

450

dsp3_start

168

dsp_irq9

270

gpio15

464

dsp1_busy

169

dsp_irq10

271

gpio16

465

dsp2_busy

170

dsp_irq11

320

Timer1

466

dsp3_busy

171

dsp_irq12

321

Timer2

480

mif1_done

172

dsp_irq13

322

Timer3

496

mif1_block

Table 4-32. Event Logger Input Sources (Cont.)

Description

Edge

Description

Edge

Description

Edge

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