CS47L35 datasheet(102/300 Pages) CIRRUS

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102

DS1085F3

CS47L35

4.5 DSP Peripheral Control

The maximum count value of the timer is determined by the TIMERn_MAX_COUNT field. This is the final count value

(when counting up), or the initial count value (when counting down). The current value of the timer counter can be read

from the TIMERn_CUR_COUNT field.

The timer is started by writing 1 to TIMERn_START. Note that, if the timer is already running, it restarts from its initial value.

The timer is stopped by writing 1 to TIMERn_STOP. The count direction (up or down) is selected using the TIMERn_DIR

bit.

The TIMERn_CONTINUOUS bit selects whether the timer automatically restarts after the end-of-count condition has been

reached. The TIMERn_RUNNING_STS indicates whether the timer is running, or if it has stopped.

Note that the timers should be stopped before making any changes to the respective configuration registers. The timer

configuration should only be changed when TIMERn_RUNNING_STS = 0.

The reference clock for each Timer should be configured and enabled before starting the Timer, and whenever the Timer

is running. If the reference clock is interrupted while the Timer is running, the Timer operation pauses, and resumes again

when the clock restarts. See Section 4.16 for details of the system clocks (including requirements for reconfiguring

DSPCLK while DSP peripherals are enabled).

4.5.3.3 Interrupts, GPIO, and Class D Speaker Driver Control

The timer status is an input to the interrupt control circuit and can be used to trigger an interrupt event after the final count

value is reached; see Section 4.15. Note that the interrupt does not occur immediately when the final count value is

reached; the interrupt is triggered at the point when the next update to the timer count value would be due.

The timer status can be output directly on a GPIO pin as an external indication of the timer activity. See Section 4.14 to

configure a GPIO pin for this function.

The timers can be used as a watchdog function to trigger a shutdown of the Class D speaker drivers. See Section 4.21 to

configure this function.

4.5.3.4 Timer Block Diagram and Control Registers

The timer block is shown in Fig. 4-32.

Figure 4-32. General-Purpose Timer

The timer control registers are described in Table 4-33.

f = TIMERn

count rate

If DSPCLK is enabled, and a clock

source other than DSPCLK is selected,

f ≤ DSPCLK/3, f ≤ 12MHz

Divider

TIMERn_REFCLK_DIV

Divide by 1, 2, 4, 8 … 64

except DSPCLK

Divider

TIMERn_PRESCALE

Divide by 1, 2, 4, 8 … 128

Divider

TIMERn_REFCLK_FREQ_SEL

DSPCLK / SYSCLK only

TIMERn_REFCLK_SRC

DSPCLK

32k Clock

MCLK1

MCLK2

SYSCLK

GPIO2

GPIO9

GPIO13

GPIO16

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