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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32WB50CG датащи(PDF) 107 Page - STMicroelectronics |
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STM32WB50CG датащи(HTML) 107 Page - STMicroelectronics |
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107 / 119 page  DS13047 Rev 5 107/119 STM32WB50CG STM32WB30CE Electrical characteristics 110 Table 82. SPI characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode 2.0 < VDD < 3.6 V -- 32 MHz Master transmitter mode 2.0 < VDD < 3.6 V 32 Slave receiver mode 2.0 < VDD < 3.6 V 32 Slave mode transmitter/full duplex 2.7 < VDD < 3.6 V 32(2) Slave mode transmitter/full duplex 2.0 < VDD < 3.6 V 20.5(2) tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4 x TPCLK -- - th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2 x TPCLK -- tw(SCKH) tw(SCKL) SCK high and low time Master mode TPCLK - 1.5 TPCLK TPCLK + 1 tsu(MI) Data input setup time Master mode 1.5 - - ns tsu(SI) Slave mode 1 - - th(MI) Data input hold time Master mode 5 - - th(SI) Slave mode 1 - - ta(SO) Data output access time Slave mode 9- 34 tdis(SO) Data output disable time 9 - 16 tv(SO) Data output valid time Slave mode 2.7 < VDD < 3.6 V - 14.5 15.5 ns Slave mode 2.0 < VDD < 3.6 V - 15.5 24 tv(MO) Master mode (after enable edge) - 2.5 3 th(SO) Data output hold time Slave mode (after enable edge) 8 - - th(MO) Master mode (after enable edge) 1 - - 1. Guaranteed by characterization results. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50 %. |
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