STM32WB50CG datasheet(16/119 Pages) STMICROELECTRONICS

16 / 119 page

Functional overview

STM32WB50CG STM32WB30CE

16/119

DS13047 Rev 5



Write protection (WRP): the protected area is protected against erasing and

programming. Two areas can be selected, with 4-Kbyte granularity.



Proprietary code readout protection (PCROP): two parts of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only:

it can only be reached by the STM32 CPU, as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

Two areas can be selected, with 2-Kbyte granularity. An additional option bit

(PCROP_RDP) makes possible to select if the PCROP area is erased or not when the

RDP protection is changed from Level 1 to Level 0.

A section of the Flash memory is secured for the RF subsystem CPU2, and cannot be

accessed by the host CPU1.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:



single error detection and correction



double error detection



the address of the ECC fail can be read in the ECC register

The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis.

A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.

3.3.4

Embedded SRAM

The STM32WB50CG device features 128 Kbytes of embedded SRAM, split in three blocks:



SRAM1: 64 Kbytes mapped at address 0x2000 0000



SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000,

with hardware parity check (this SRAM can be retained in Standby mode)



SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and

mirrored at 0x1000 8000 with hardware parity check

Table 2. Access status vs. readout protection level and execution modes

Area

Protection

level

User execution

Debug, boot from SRAM or boot

from system memory (loader)

Read

Write

Erase

Read

Write

Erase

Main

memory

Yes

N/A

System

memory

Yes

N/A

Option

bytes

Yes

2Yes

No(1)

1. The option byte can be modified by the RF subsystem.

No(1)

N/A

Backup

registers

1Yes

Yes

N/A(2)

2. Erased when RDP changes from Level 1 to Level 0.

N/A(2)

Yes

N/A

SRAM2a

SRAM2b

Yes

Yes(2)

No(2)

Yes

N/A

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