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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32WB50CG датащи(PDF) 86 Page - STMicroelectronics |
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STM32WB50CG датащи(HTML) 86 Page - STMicroelectronics |
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86 / 119 page  Electrical characteristics STM32WB50CG STM32WB30CE 86/119 DS13047 Rev 5 6.3.12 PLL characteristics The parameters given in Table 57 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 20: General operating conditions. Table 57. PLL characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(2) -2.66 - 16 MHz PLL input clock duty cycle - 45 - 55 % fPLL_P_OUT PLL multiplier output clock P - 2 - 64 MHz fPLL_Q_OUT PLL multiplier output clock Q - 8 - 64 fPLL_R_OUT PLL multiplier output clock R - 8 - 64 fVCO_OUT PLL VCO output - 96 - 344 tLOCK PLL lock time - - 15 40 μs Jitter RMS cycle-to-cycle jitter System clock 64 MHz -40 - ps RMS period jitter - 30 - IDD(PLL) PLL power consumption on VDD(1) VCO freq = 96 MHz - 200 260 μA VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 1. Guaranteed by design. 2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the two PLLs. |
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