STM32WB50CG datasheet(17/119 Pages) STMICROELECTRONICS

17 / 119 page

DS13047 Rev 5

17/119

STM32WB50CG STM32WB30CE

Functional overview

The STM32WB30CG device features 96 Kbytes of embedded SRAM, split in three blocks:



SRAM1: 32 Kbytes mapped at address 0x2000 0000



SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000,

with hardware parity check (this SRAM can be retained in Standby mode)



SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and

mirrored at 0x1000 8000 with hardware parity check

SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the

SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the

host CPU1.

The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock

speeds.

3.4

Security and safety

The STM32WB50CG and STM32WB30CE contain many security blocks both for the BLE or

IEEE 802.15.4 and the Host application.

It includes:



Customer storage of the BLE or 802.15.4 keys



Secure Flash memory partition for RF subsystem-only access



Secure SRAM partition, that can be accessed only by the RF subsystem



True random number generator (RNG)



Advance encryption standard hardware accelerators (AES-256bit, supporting chaining

modes ECB, CBC, CTR, GCM, GMAC, CCM)



Private key acceleration (PKA) including:

–

Modular arithmetic including exponentiation with maximum modulo size of 3136

bits

–

Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA

verification with maximum modulo size of 521 bits



Cyclic redundancy check calculation unit (CRC)

A specific mechanism is in place to ensure that all the code executed by the RF subsystem

CPU2 can be secure, whatever the Host application.

3.5

Boot modes and FW update

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:



Boot from user Flash



Boot from system memory



Boot from embedded SRAM

The devices always boot on CPU1 core. The embedded bootloader code makes it possible

to boot from various peripherals:



UART



I2C



SPI

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