STM32WB50CG datasheet(26/119 Pages) STMICROELECTRONICS

26 / 119 page

Functional overview

STM32WB50CG STM32WB30CE

26/119

DS13047 Rev 5

low-power run mode. The RF subsystem is not available in this mode and must be

OFF.



Stop 0, Stop 1 and Stop 2

Stop modes achieve the lowest power consumption while retaining the content of all

the SRAM and registers. The LSE (or LSI) is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop modes

to detect their wakeup condition.

Three modes are available: Stop 0, Stop 1 and Stop 2. In Stop 2 mode, most of the

VCORE domain is put in a lower leakage mode.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller

wakeup time but a higher consumption than Stop 2. In Stop 0 mode the main regulator

remains ON, allowing a very fast wakeup time but with higher consumption.

In these modes the RF subsystem can wait for incoming events in all Stop modes.

The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI

up to 48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem is used

the exits must be set to HSI16 only.



Standby

The Standby mode is used to achieve the lowest power consumption with BOR. The

internal regulator is switched off so that the VCORE domain is powered off.

The RTC can remain active (Standby mode with RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with

internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1, SRAM2b and register contents are lost except

for registers in the Backup domain and Standby circuitry. Optionally, SRAM2a can be

retained in Standby mode, supplied by the low-power regulator (Standby with 32 KB

SRAM2a retention mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset,

WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,

periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE, or

from the RF system wakeup).

The system clock after wakeup is 16 MHz, derived from the HSI16.

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