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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX6SDLCEC датащи(PDF) 118 Page - NXP Semiconductors |
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IMX6SDLCEC датащи(HTML) 118 Page - NXP Semiconductors |
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118 / 169 page  i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 118 NXP Semiconductors Electrical Characteristics Figure 83. MLB 6-Pin Delay, Setup, and Hold Times 4.11.15 PCIe PHY Parameters The PCIe interface complies with PCIe specification Gen2 x1 lane and supports the PCI Express 1.1/2.0 standard. Table 77. MLB 6-Pin Interface Timing Parameters Parameter Symbol Min Max Unit Comment Cycle-to-cycle system jitter tjitter — 600 ps — Transmitter MLB_SIG_P/_N (MLB_DATA_P/_N) output valid from transition of MLB_CLK_P/_N (low-to-high)1 1 t delay, tphz, tplz, tsu, and thd may also be referenced from a low-to-high transition of the recovered clock for 2:1 and 4:1 recov- ered-to-external clock ratios. tdelay 0.6 1.3 ns — Disable turnaround time from transition of MLB_CLK_P/_N (low-to-high) tphz 0.6 3.5 ns — Enable turnaround time from transition of MLB_CLK_P/_N (low-to-high) tplz 0.6 5.6 ns — MLB_SIG_P/_N (MLB_DATA_P/_N) valid to transition of MLB_CLK_P/_N (low-to-high) tsu 0.05 — ns — MLB_SIG_P/_N (MLB_DATA_P/_N) hold from transition of MLB_CLK_P/_N (low-to-high)2 2 The transmitting device must ensure valid data on MLB_SIG_P/_N (MLB_DATA_P/_N) for at least t hd(min) following the rising edge of MLB_CLK_P/N; receivers must latch MLB_SIG_P/_N (MLB_DATA_P/_N) data within thd(min) of the rising edge of ML- B_CLK_P/_N. thd 0.6 — |
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