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IMX6SDLCEC датащи(PDF) 116 Page - NXP Semiconductors

номер детали IMX6SDLCEC
подробное описание детали  i.MX 6Solo/6DualLite Applications Processors for Consumer Products
PDF  169 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
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IMX6SDLCEC датащи(HTML) 116 Page - NXP Semiconductors

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i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018
116
NXP Semiconductors
Electrical Characteristics
4.11.14.2 MediaLB (MLB) Controller AC Timing Electrical Specifications
This section describes the timing electrical information of the MediaLB module. Figure 82 show the
timing of MediaLB 3-pin interface, and Table 75 and Table 76 lists the MediaLB 3-pin interface timing
characteristics.
Figure 82. MediaLB 3-Pin Timing
Ground = 0.0 V; Load Capacitance = 60 pF; MediaLB speed = 256/512 Fs; Fs = 48 kHz; all timing
parameters specified from the valid voltage threshold as listed below; unless otherwise noted.
Table 75. MLB 256/512 Fs Timing Parameters
Parameter
Symbol
Min
Max
Unit
Comment
MLB_CLK operating frequency1
fmck
11.264
25.6
MHz
256xFs at 44.0 kHz
512xFs at 50.0 kHz
MLB_CLK rise time
tmckr
—3
ns
VIL TO VIH
MLB_CLK fall time
tmckf
—3
ns
VIH TO VIL
MLB_CLK low time2
tmckl
30
14
—
ns
256xFs
512xFs
MLB_CLK high time
tmckh
30
14
—
ns
256xFs
512xFs
MLB_SIG/MLB_DATA receiver input valid to
MLB_CLK falling
tdsmcf
1—
ns
—
MLB_SIG/MLB_DATA receiver input hold
from MLB_CLK low
tdhmcf
tmdzh
—ns
—
MLB_SIG/MLB_DATA output high impedance
from MLB_CLK low
tmcfdz
0tmckl
ns
3
Bus Hold from MLB_CLK low
tmdzh
4—
ns
—



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