IMX6SDLCEC datasheet(12/169 Pages) NXP

12 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Modules List

CSU

Central Security Unit

Security

The Central Security Unit (CSU) is responsible for

setting comprehensive security policy within the i.MX

6Solo/6DualLite platform.

CTI-0

CTI-1

CTI-2

CTI-3

CTI-4

Cross Trigger Interfaces

Debug / Trace

Cross Trigger Interfaces allows cross-triggering based

on inputs from masters attached to CTIs. The CTI

module is internal to the Cortex-A9 Core Platform.

CTM

Cross Trigger Matrix

Debug / Trace

Cross Trigger Matrix IP is used to route triggering events

between CTIs. The CTM module is internal to the

Cortex-A9 Core Platform.

DAP

Debug Access Port

System Control

Peripherals

The DAP provides real-time access for the debugger

without halting the core to:

• System memory and peripheral registers

• All debug configuration registers

The DAP also provides debugger access to JTAG scan

chains. The DAP module is internal to the Cortex-A9

Core Platform.

DCIC-0

DCIC-1

Display Content Integrity

Checker

Automotive IP

The DCIC provides integrity check on portion(s) of the

display. Each i.MX 6Solo/6DualLite processor has two

such modules.

DSI

MIPI DSI i/f

Multimedia

Peripherals

The MIPI DSI IP provides DSI standard display port

interface. The DSI interface support 80 Mbps to 1 Gbps

speed per data lane.

DTCP

Multimedia

Peripherals

Provides encryption function according to Digital

Transmission Content Protection standard for traffic

over MLB150.

eCSPI1-4

Configurable SPI

Connectivity

Peripherals

Full-duplex enhanced Synchronous Serial Interface. It is

configurable to support Master/Slave modes, four chip

selects to support multiple peripherals.

ENET

Ethernet Controller

Connectivity

Peripherals

The Ethernet Media Access Controller (MAC) is

designed to support 10/100/1000 Mbps Ethernet/IEEE

802.3 networks. An external transceiver interface and

transceiver function are required to complete the

interface to the media. The module has dedicated

hardware to support the IEEE 1588 standard. See the

ENET chapter of the reference manual for details.

Note: The theoretical maximum performance of 1 Gbps

ENET is limited to 470 Mbps (total for Tx and Rx) due to

internal bus throughput limitations. The actual

measured performance in optimized environment is up

to 400 Mbps. For details, see the ERR004512 erratum

in the i.MX 6Solo/6DualLite errata document

(IMX6SDLCE).

Table 2. i.MX 6Solo/6DualLite Modules List (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

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