IMX6SDLCEC datasheet(27/169 Pages) NXP

27 / 169 page

Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

GPIO supply

voltages8

NVCC_CSI,

NVCC_EIM,

NVCC_ENET,

NVCC_GPIO,

NVCC_LCD,

NVCC_NANDF,

NVCC_SD1,

NVCC_SD2,

NVCC_SD3,

NVCC_JTAG

1.65

1.8,

2.8,

3.3

3.6

—

NVCC_LVDS_2P59

NVCC_MIPI

2.25

2.5

2.75

—

HDMI supply voltages

HDMI_VP

0.99

1.1

1.3

—

HDMI_VPH

2.25

2.5

2.75

—

PCIe supply voltages

PCIE_VP

1.023

1.1

1.21

—

PCIE_VPH

2.325

2.5

2.75

—

PCIE_VPTX

1.023

1.1

1.21

—

Junction temperature

Extended commercial

-20

—

105

oCSee i.MX 6Solo/6DualLite Product Lifetime

Usage Estimates Application Note, AN4725,

for information on product lifetime for this

processor.

Junction temperature

Standard commercial

0—

oCSee i.MX 6Solo/6DualLite Product Lifetime

Usage Estimates Application Note, AN4725,

for information on product lifetime for this

processor.

1 Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set

point = (Vmin + the supply tolerance). This results in an optimized power/speed ratio.

2 See the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

(IMX6DQ6SDLHDG) for bypass capacitors requirements for each of the *_CAP supply outputs.

3 VDD_ARM_IN and VDD_SOC_IN must be 125 mV higher than the LDO Output Set Point for correct regulator supply voltage.

4 In LDO enabled mode, the internal LDO output set points must be configured such that the:

• VDD_ARM LDO output set point does not exceed the VDD_SOC LDO output set point by more than 100 mV.

• VDD_SOC LDO output set point is equal to the VDD_PU LDO output set point.

The VDD_ARM LDO output set point can be lower than the VDD_SOC LDO output set point, however, the minimum output set

points shown in this table must be maintained.

5 In LDO bypassed mode, the external power supply must ensure that VDD_ARM_IN does not exceed VDD_SOC_IN by more

than 100 mV. The VDD_ARM_IN supply voltage can be lower than the VDD_SOC_IN supply voltage. The minimum voltages

shown in this table must be maintained.

6 When using VDD_SOC_CAP to supply the PCIE_VP and PCIE_VPTX, the maximum setting is 1.175V. If VDD_SOC_CAP

requires setting to 1.2V or higher, the PCIE_VP and PCIE_VPTX must use an external supply to guarantee not to exceed the

1.21V maximum operating voltage.

7 While setting VDD_SNVS_IN voltage with respect to Charging Currents and RTC, refer to Hardware Development Guide for i.MX

6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).

8 All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or not

and associated IO pins need to have a pull-up or pull-down resistor applied to limit any non-connected gate current.

9 This supply also powers the pre-drivers of the DDR IO pins, hence, it must be always provided, even when LVDS is not used.

Table 8. Operating Ranges (continued)

Parameter

Description

Symbol

Min

Typ

Max1

Unit

Comment2

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