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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX6SDLCEC датащи(PDF) 91 Page - NXP Semiconductors |
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IMX6SDLCEC датащи(HTML) 91 Page - NXP Semiconductors |
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91 / 169 page  Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 NXP Semiconductors 91 Figure 58. TMDS Output Signals Rise and Fall Time Definition Table 62. Switching Characteristics Symbol Parameter Conditions Min Typ Max Unit TMDS Drivers Specifications — Maximum serial data rate — — — 3.4 Gbps F TMDSCLK TMDSCLK frequency On TMDSCLKP/N outputs 25 — 340 MHz P TMDSCLK TMDSCLK period RL = 50 Ω See Figure 54. 2.94 — 40 ns t CDC TMDSCLK duty cycle t CDC = t CPH / P TMDSCLK RL = 50 Ω See Figure 54. 40 50 60 % t CPH TMDSCLK high time RL = 50 Ω See Figure 54. 45 6 UI1 1 UI means TMDS clock unit. t CPL TMDSCLK low time RL = 50 Ω See Figure 54. 45 6 UI1 — TMDSCLK jitter2 2 Relative to ideal recovery clock, as specified in the HDMI specification, version 1.4a, section 4.2.3. RL = 50 Ω — — 0.25 UI1 t SK(p) Intra-pair (pulse) skew RL = 50 Ω See Figure 56. — — 0.15 UI1 t SK(pp) Inter-pair skew RL = 50 Ω See Figure 57. —— 1 UI1 tR Differential output signal rise time 20–80% RL = 50 Ω See Figure 58. 75 — 0.4 UI ps tF Differential output signal fall time 20–80% RL = 50 Ω See Figure 58. 75 — 0.4 UI ps — Differential signal overshoot Referred to 2x VSWING —— 15 % — Differential signal undershoot Referred to 2x VSWING —— 25 % |
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