IMX6SDLCEC datasheet(48/169 Pages) NXP

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i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

4.7.4

MLB I/O AC Parameters

The differential output transition time waveform is shown in Figure 8.

Figure 8. Differential MLB Driver Transition Time Waveform

A 4-stage pipeline is utilized in the MLB 6-pin implementation in order to facilitate design, maximize

throughput, and allow for reasonable PCB trace lengths. Each cycle is one ipp_clk_in* (internal clock from

MLB PLL) clock period. Cycles 2, 3, and 4 are MLB PHY related. Cycle 2 includes clock-to-output delay

of Signal/Data sampling flip-flop and Transmitter, Cycle 3 includes clock-to-output delay of Signal/Data

clocked receiver, Cycle 4 includes clock-to-output delay of Signal/Data sampling flip-flop.

MLB 6-pin pipeline diagram is shown in Figure 9.

Table 33. I/O AC Parameters of LVDS Pad

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Differential pulse skew1

1 t

SKD = | tPHLD -tPLHD |, is the magnitude difference in differential propagation delay time between the positive going edge and

the negative going edge of the same channel.

tSKD

Rload = 100

Ω,

Cload = 2 pF

—

0.25

Transition Low to High Time2

2 Measurement levels are 20-80% from output voltage.

tTLH

——

0.5

Transition High to Low Time2

tTHL

——

0.5

Operating Frequency

—

600

800

MHz

Offset voltage imbalance

Vos

—

150

padp

padn

VDIFF

0V (Differential)

VDIFF = {padp} - {padn}

tTLH

20%

80%

20%

80%

tTHL

VOH

VOL

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