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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX6SDLCEC датащи(PDF) 81 Page - NXP Semiconductors |
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IMX6SDLCEC датащи(HTML) 81 Page - NXP Semiconductors |
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81 / 169 page  Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 NXP Semiconductors 81 4.11.4.3 SDR50/SDR104 AC Timing Figure 42 depicts the timing of SDR50/SDR104, and Table 54 lists the SDR50/SDR104 timing characteristics. Figure 42. SDR50/SDR104 Timing 4.11.4.4 Bus Operation Condition for 3.3 V and 1.8 V Signaling Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50 mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are identical to those shown in Table 23, "GPIO DC Parameters," on page 40. Table 54. SDR50/SDR104 Interface Timing Specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock Frequency Period tCLK 4.8 — ns SD2 Clock Low Time tCL 0.46 × tCLK 0.54 × tCLK ns SD3 Clock High Time tCH 0.46 × tCLK 0.54 × tCLK ns uSDHC Output/Card Inputs SDx_CMD, SDx_DATAx in SDR50 (Reference to CLK) SD4 uSDHC Output Delay tOD –3 1 ns uSDHC Output/Card Inputs SDx_CMD, SDx_DATAx in SDR104 (Reference to CLK) SD5 uSDHC Output Delay tOD –1.6 0.74 ns uSDHC Input/Card Outputs SDx_CMD, SDx_DATAx in SDR50 (Reference to CLK) SD6 uSDHC Input Setup Time tISU 2.5 — ns SD7 uSDHC Input Hold Time tIH 1.5 — ns uSDHC Input/Card Outputs SDx_CMD, SDx_DATAx in SDR104 (Reference to CLK)1 1Data window in SDR100 mode is variable. SD8 Card Output Data Window tODW 0.5 × tCLK —ns |
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