IMX6SDLCEC datasheet(30/169 Pages) NXP

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i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

4.1.6

Low Power Mode Supply Currents

Table 11 shows the current core consumption (not including I/O) of i.MX 6Solo/6DualLite processors in

selected low power modes.

NVCC_LVDS2P56

—

NVCC_LVDS2P5 is connected to

VDD_HIGH_CAP at the board level.

VDD_HIGH_CAP is capable of

handing the current required by

NVCC_LVDS2P5.

—

MISC

DDR_VREF

—

1 The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the

VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_LVDS_2P5, NVCC_MIPI, or

HDMI and PCIe VPH supplies).

2 Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown in Table 10. The maximum

VDD_SNVS_IN current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal

to 00, or use of the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of

sourcing that current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.

3 This is the maximum current per active USB physical interface.

4 The DRAM power consumption is dependent on several factors, such as external signal termination. DRAM power calculators

are typically available from the memory vendors. They take in account factors, such as signal termination. See the i.MX

6Solo/DualLite Power Consumption Measurement Application Note (AN4576) for examples of DRAM power consumption

during specific use case scenarios.

5 General equation for estimated, maximum power consumption of an IO power supply:

Imax = N x C x V x (0.5 x F)

Where:

N—Number of IO pins supplied by the power line

C—Equivalent external capacitive load

V—IO voltage

(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)

In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.

6 NVCC_LVDS2P5 is supplied by VDD_HIGH_CAP (by external connection) so the maximum supply current is included in the

current shown for VDD_HIGH_IN. The maximum supply current for NVCC_LVDS2P5 has not been characterized separately.

Table 11. Stop Mode Current and Power Consumption

Mode

Test Conditions

Supply

Typical1

Units

WAIT

• Arm, SoC, and PU LDOs are set to 1.225

• HIGH LDO set to 2.5 V

• Clocks are gated.

• DDR is in self refresh.

• PLLs are active in bypass (24MHz)

• Supply Voltages remain ON

VDD_ARM_IN (1.4V)

4.5

VDD_SOC_IN (1.4V)

VDD_HIGH_IN (3.0V)

13.5

Total

Table 10. Maximum Supply Currents (continued)

Power Line

Conditions

Max Current

Unit

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