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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX6SDLCEC датащи(PDF) 37 Page - NXP Semiconductors |
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IMX6SDLCEC датащи(HTML) 37 Page - NXP Semiconductors |
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37 / 169 page  Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 NXP Semiconductors 37 4.4.3 Ethernet PLL 4.4.4 480 MHz PLL 4.4.5 MLB PLL The MediaLB PLL is necessary in the MediaLB 6-Pin implementation to phase align the internal and external clock edges, effectively tuning out the delay of the differential clock receiver and is also responsible for generating the higher speed internal clock, when the internal-to-external clock ratio is not 1:1. Reference clock 24 MHz Lock time <11250 reference cycles Table 17. Ethernet PLL’s Electrical Parameters Parameter Value Clock output range 500 MHz Reference clock 24 MHz Lock time <11250 reference cycles Table 18. 480 MHz PLL’s Electrical Parameters Parameter Value Clock output range 480 MHz PLL output Reference clock 24 MHz Lock time <383 reference cycles Table 19. MLB PLL’s Electrical Parameters Parameter Value Lock time <1 ms Table 16. 528 MHz PLL’s Electrical Parameters (continued) Parameter Value |
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