IMX6SDLCEC datasheet(80/169 Pages) NXP

80 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

4.11.4.2 eMMC4.4/4.41 (Dual Data Rate) AC Timing

Figure 41 depicts the timing of eMMC4.4/4.41. Table 53 lists the eMMC4.4/4.41 timing characteristics.

Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).

Figure 41. eMMC4.4/4.41 Timing

uSDHC Input/Card Outputs SDx_CMD, SDx_DATAx (Reference to CLK)

SD7

uSDHC Input Setup Time

tISU

2.5

—

SD8

uSDHC Input Hold Time4

tIH

1.5

—

1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

2 In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0

–50 MHz.

3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0

–52 MHz.

4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

Table 53. eMMC4.4/4.41 Interface Timing Specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock1

1 1 Clock duty cycle will be in the range of 47% to 53%.

SD1

Clock Frequency (eMMC4.4/4.41 DDR)

fPP

052

MHz

SD1

Clock Frequency (SD3.0 DDR)

fPP

050

MHz

uSDHC Output / Card Inputs SDx_CMD, SDx_DATAx (Reference to CLK)

SD2

uSDHC Output Delay

tOD

2.8

6.8

uSDHC Input / Card Outputs SDx_CMD, SDx_DATAx (Reference to CLK)

SD3

uSDHC Input Setup Time

tISU

1.7

—

SD4

uSDHC Input Hold Time

tIH

1.5

—

Table 52.

SD/eMMC4.3 Interface Timing Specification (continued)

Parameter

Symbols

Min

Max

Unit

SD1

SD2

SD3

Output from eSDHCv3 to card

Input from card to eSDHCv3

SDx_DATA[7:0]

SDx_CLK

SD4

SD2

......

SDx_DATA[7:0]

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