IMX6SDLCEC datasheet(22/169 Pages) NXP

22 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Modules List

DRAM_VREF

When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the

NVCC_DRAM supply. The user must tie DDR_VREF to a precision external resistor divider. Use a

Ω 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_DRAM. Shunt each resistor with a

closely-mounted 0.1 µF capacitor.

To reduce supply current, a pair of 1.5 k

Ω 0.1% resistors can be used. Using resistors with

recommended tolerances ensures the ± 2% DDR_VREF tolerance (per the DDR3 specification) is

maintained when four DDR3 ICs plus the i.MX 6Solo/6DualLite are drawing current on the resistor

divider.

It is recommended to use regulated power supply for “big” memory configurations (more that eight

devices).

ZQPAD

DRAM calibration resistor 240

Ω 1% used as reference during DRAM output buffer driver

calibration should be connected between this pad and GND.

NVCC_LVDS_2P5

The DDR pre-drivers share the NVCC_LVDS_2P5 ball with the LVDS interface. This ball can be

shorted to VDD_HIGH_CAP on the circuit board.

VDD_FA

FA_ANA

These signals are reserved for NXP manufacturing use only. User must tie both connections to

GND.

GPANAIO

Analog output for NXP use only. This output must remain unconnected.

JTAG_nnnn

The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated

if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

must be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX 6Solo/6DualLite reference manual. Both

names refer to the same signal. JTAG_MOD must be externally connected to GND for normal

operation. Termination to GND through an external pull-down resistor (such as 1 k

Ω) is allowed.

JTAG_MOD set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard.

JTAG_MOD set to low configures the JTAG interface for common SW debug adding all the system

TAPs to the chain.

These signals are not functional and must remain unconnected by the user.

SRC_POR_B

This cold reset negative logic input resets all modules and logic in the IC.

ONOFF

In normal mode may be connected to ON/OFF button (De-bouncing provided at this input).

Internally this pad is pulled up. Short connection to GND in OFF mode causes internal power

management state machine to change state to ON. In ON mode short connection to GND

generates interrupt (intended to SW controllable power down). Long above ~5s connection to GND

causes “forced” OFF.

TEST_MODE

TEST_MODE is for NXP factory use. This signal is internally connected to an on-chip pull-down

device. This signal must either be tied to Vss or remain unconnected.

PCIE_REXT

The impedance calibration process requires connection of reference resistor 200

Ω 1% precision

resistor on PCIE_REXT pad to ground.

CSI_REXT

MIPI CSI PHY reference resistor. Use 6.04 K

Ω 1% resistor connected between this pad and GND

DSI_REXT

MIPI DSI PHY reference resistor. Use 6.04 K

Ω 1% resistor connected between this pad and GND

Table 3. Special Signal Considerations (continued)

Signal Name

Remarks

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