IMX6SDLCEC datasheet(115/169 Pages) NXP

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Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

115

Table 74 lists the MediaLB 6-pin interface electrical characteristics.

Table 74. MediaLB 6-Pin Interface Electrical DC Specifications

Parameter

Symbol

Test Conditions

Min

Max

Unit

Driver Characteristics

Differential output voltage

(steady-state):

I VO+ - VO- I

VOD

See Note1

1 The signal-ended output voltage of a driver is defined as V

O+ on MLB_CLK_P, MLB_SIG_P, and MLB_DATA_P. The

signal-ended output voltage of a driver is defined as VO- on MLB_CLK_N, MLB_SIG_N, and MLB_DATA_N.

300

500

Difference in differential output

voltage between (high/low)

steady-states:

I VOD, high - VOD, low I

ΔVOD

—

-50

Common-mode output voltage:

(VO+ - VO-) / 2

VOCM

—1.0

1.5

Difference in common-mode

output between (high/low)

steady-states:

I VOCM, high - VOCM, low I

ΔVOCM

—

-50

Variations on common-mode

output during a logic state

transitions

VCMV

See Note2

2 Variations in the common-mode voltage can occur between logic states (for example, during state transitions) as a result of

differences in the transition rate of VO+ and VO-.

—150

mVpp

Short circuit current

|IOS|

See Note3

3 Short circuit current is applicable when V

O+ and VO- are shorted together and/or shorted to ground.

—43

Differential output impedance

—1.6

—

Receiver Characteristics

Differential clock input:

• logic low steady-state

• logic high steady-state

• hysteresis

VILC

VIHC

VHSC

See Note4

4 The logic state of the receiver is undefined when -50 mV < V

ID < 50 mV.

—

-25

-50

—

Differential signal/data input:

• logic low steady-state

• logic high steady-state

VILS

VIHS

—

-50

—

Signal-ended input voltage

(steady-state):

• MLB_SIG_P, MLB_DATA_P

• MLB_SIG_N, MLB_DATA_N

VIN+

VIN-

—

0.5

2.0

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