IMX6SDLCEC datasheet(63/169 Pages) NXP

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Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

4.9.4

Multi-Mode DDR Controller (MMDC)

The Multi-Mode DDR Controller is a dedicated interface to DDR3/DDR3L/LPDDR2 SDRAM.

4.9.4.1

MMDC Compatibility with JEDEC-compliant SDRAMs

The i.MX 6Solo/6DualLite MMDC supports the following memory types:

•

LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009

•

DDR3/DDR3L SDRAM compliant to JESD79-3D DDR3 JEDEC standard release April, 2008

MMDC operation with the standards stated above is contingent upon the board DDR design adherence to

the DDR design and layout requirements stated in the Hardware Development Guide for i.MX 6Quad,

6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

4.9.4.2

MMDC Supported DDR3/DDR3L/LPDDR2 Configurations

Table 44 and Table 45 show the supported DDR3/DDR3L/LPDDR2 configurations.

WE47

EIM_DTACK_B Active to

EIM_CSx_B Invalid

MAXCO - MAXCSO + MAXDTI

MAXCO -

MAXCSO +

MAXDTI

—ns

WE48

EIM_CSx_B Invalid to

EIM_DTACK_B Invalid

—

1 For more information on configuration parameters mentioned in this table, see the i.MX 6Solo/6DualLite reference manual.

2 In this table, CSA means WCSA when write operation or RCSA when read operation.

3 In this table, CSN means WCSN when write operation or RCSN when read operation.

4 t is ACLK_EIM_SLOW_CLK_ROOT cycle time.

5 In this table, ADVN means WADVN when write operation or RADVN when read operation.

6 In this table, ADVA means WADVA when write operation or RADVA when read operation.

Table 44. i.MX 6Solo Supported DDR3/DDR3L/LPDDR2 Configurations

Parameter

LPDDR2

DDR3

DDR3L

Clock frequency

400 MHz

Bus width

16/32-bit

Channel

Single

Chip selects

Table 43. EIM Asynchronous Timing Parameters Table Relative Chip to Select (continued)

Ref No.

Parameter

Determination by

Synchronous measured

parameters1

Min

Max

Unit

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