AD9520-1SLASHPCBZ datasheet(78/80 Pages) AD

78 / 80 page

AD9520-1

Data Sheet

Rev. B | Page 78 of 80

LVPECL CLOCK DISTRIBUTION

The LVPECL outputs of the AD9520-1 provide the lowest jitter

clock signals available from the AD9520-1. The LVPECL

outputs (because they are open emitter) require a dc

termination to bias the output transistors. The simplified

equivalent circuit in Figure 54 shows the LVPECL output stage.

In most applications, an LVPECL far-end Thevenin termination

(see Figure 71) or Y-termination (see Figure 72) is recommended.

In both cases, VS of the receiving buffer should match the VS_DRV. If

it does not, ac coupling is recommended (see Figure 73).

VS_DRV

LVPECL

50Ω

SINGLE-ENDED

(NOT COUPLED)

VS_DRV

LVPECL

127Ω

83Ω

Figure 71. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination

VS_DRV

LVPECL

Z0 = 50Ω

VS = VS_DRV

LVPECL

50Ω

Z0 = 50Ω

Figure 72. DC-Coupled 3.3 V LVPECL Y-Termination

VS_DRV

LVPECL

100Ω DIFFERENTIAL

(COUPLED)

TRANSMISSION LINE

LVPECL

100Ω

0.1nF

200Ω

Figure 73. AC-Coupled LVPECL with Parallel Transmission Line

LVPECL Y-Termination

LVPECL Y-termination is an elegant termination scheme that

uses the fewest components and offers both odd- and even-mode

impedance matching. Even-mode impedance matching is an

important consideration for closely coupled transmission lines

at high frequencies. Its main drawback is that it offers limited

flexibility for varying the drive strength of the emitter-follower

LVPECL driver. This can be an important consideration when

driving long trace lengths but is usually not an issue. In the case

where VS_DRV = 2.5 V, the 50 Ω termination resistor connected to

ground in Figure 72 should be changed to 19 Ω.

Far-End Thevenin Termination

Far-end Thevenin termination uses a resistor network to

provide 50 Ω termination to a dc voltage that is below VOL of

the LVPECL driver. In this case, VS_DRV on the AD9520-1 should

equal VS of the receiving buffer. Although the resistor combination

shown results in a dc bias point of VS_DRV − 2 V, the actual common-

mode voltage is VS_DRV − 1.3 V because there is additional current

flowing from the AD9520-1 LVPECL driver through the pull-

down resistor.

The circuit is identical for the case where VS_DRV = 2.5 V, except that

the pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.

CMOS CLOCK DISTRIBUTION

The output drivers of the AD9520-1 can be configured as

CMOS drivers. When selected as a CMOS driver, each output

becomes a pair of CMOS outputs, each of which can be

individually turned on or off and set as inverting or

noninverting. These outputs are 3.3 V or 2.5 V CMOS

compatible. However, every output driver (including the

LVPECL drivers) must be run at either 2.5 V or 3.3 V. The user

cannot mix and match 2.5 V and 3.3 V outputs.

When using single-ended CMOS clocking, consider the following

guidelines:

•

Using the CMOS drivers in the same output channel group

as the LVPECL drivers may result in performance degradation

of the LVPECL drivers. Where possible, program the two

CMOS drivers that form the same output of a differential

pair to be out of phase such that one driver is high while

the other is low. It is recommended that the evaluation

board be used to verify the performance of the AD9520-1

in demanding applications where both CMOS and

LVPECL drivers are in the same group, and the very best

jitter performance is required.

•

If possible, design point-to-point connections such that

each driver has only one receiver. Connecting outputs in

this manner allows for simple termination schemes and

minimizes ringing due to possible mismatched impedances

on the output trace. Series termination at the source is

generally required to provide transmission line matching

and/or to reduce current transients at the driver.

•

The value of the resistor is dependent on the board design

and timing requirements (typically 10 Ω to 100 Ω is used).

CMOS outputs are also limited in terms of the capacitive

load or trace length that they can drive. Typically, trace

lengths of less than 3 inches are recommended to preserve

signal rise/fall times and signal integrity.

CMOS

10Ω

60.4Ω

(1.0 INCH)

MICROSTRIP

Figure 74. Series Termination of CMOS Output

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