AD9520-1SLASHPCBZ datasheet(71/80 Pages) AD

71 / 80 page

Data Sheet

AD9520-1

Rev. B | Page 71 of 80

Table 55. Output Driver Control

Reg.

Addr.

(Hex) Bits

Name

Description

0x0F0 7

OUT0 format

Selects the output type for OUT0.

0: LVPECL (default).

1: CMOS.

[6:5] OUT0 CMOS

configuration

Sets the CMOS output configuration for OUT0 when Register 0x0F0[7] = 1b.

Bits[6:5]

OUT0A

OUT0B

11 (default)

Tristate

[4:3] OUT0 polarity

Sets the output polarity for OUT0.

Bit 7

Bit 4

Bit 3

Output Type

OUT0A

OUT0B

0 (default)

LVPECL

CMOS

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

[2:1] OUT0 LVPECL

differential

voltage

Sets the LVPECL output differential voltage (VOD).

Bit 2

Bit 1

VOD (mV)

1 (default)

0 (default)

400

600

780

960

OUT0 LVPECL

power-down

LVPECL power-down.

0: normal operation (default).

1: safe power-down.

0x0F1 [7:0] OUT1 control

This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.

0x0F2 [7:0] OUT2 control

This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.

0x0F3 [7:0] OUT3 control

This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.

0x0F4 [7:0] OUT4 control

This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.

0x0F5 [7:0] OUT5 control

This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.

0x0F6 [7:0] OUT6 control

This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.

0x0F7 [7:0] OUT7 control

This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.

0x0F8 [7:0] OUT8 control

This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.

0x0F9 [7:0] OUT9 control

This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.

0x0FA [7:0] OUT10 control

This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.

0x0FB [7:0] OUT11 control

This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.

0x0FC 7

CSDLD en OUT7

OUT7 is enabled only if the CSDLD signal is high.

Bit 7

CSDLD

Signal

OUT7 Enable Status

Not affected by CSDLD signal (default).

Asynchronous power-down.

Asynchronously enables OUT7 if not powered down by other settings. For this feature, use current

source digital lock detect and set the enable LD pin comparator bit (Register 0x01D[3]).

CSDLD en OUT6

OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

CSDLD en OUT5

OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

CSDLD en OUT4

OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

CSDLD en OUT3

OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

CSDLD en OUT2

OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

CSDLD en OUT1

OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

CSDLD en OUT0

OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0x0FD [7:4] Unused

Unused.

CSDLD en OUT11 OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

CSDLD en OUT10 OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

CSDLD en OUT9

OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

CSDLD en OUT8

OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

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