AD9520-1SLASHPCBZ datasheet(40/80 Pages) AD

40 / 80 page

AD9520-1

Data Sheet

Rev. B | Page 40 of 80

A flowchart of the automatic/internal holdover function

operation is shown in Figure 47.

YES

PLL ENABLED

DLD == LOW

WAS

LD PIN == HIGH

WHEN DLD WENT

LOW?

HIGH IMPEDANCE

CHARGE PUMP

REFERENCE

EDGE AT PFD?

RELEASE

CHARGE PUMP

HIGH IMPEDANCE

DLD == HIGH

YES

LOOP OUT OF LOCK. DIGITAL LOCK

DETECT SIGNAL GOES LOW WHEN THE

LOOP LEAVES LOCK, AS DETERMINED

BY THE PHASE DIFFERENCE AT THE

INPUT OF THE PFD.

REG 0x01D[3]: LD PIN COMPARATOR ENABLE.

0b = DISABLE; 1b = ENABLE. WHEN DISABLED,

THE HOLDOVER FUNCTION ALWAYS SENSES

THE LD PIN AS HIGH.

CHARGE PUMP IS MADE HIGH IMPEDANCE.

PLL COUNTERS CONTINUE

OPERATING NORMALLY.

CHARGE PUMP REMAINS HIGH IMPEDANCE

UNTIL THE REFERENCE RETURNS.

TAKE CHARGE PUMP OUT OF

HIGH IMPEDANCE. PLL CAN NOW RESETTLE.

WAIT FOR DLD TO GO HIGH. THIS TAKES

5 TO 255 CYCLES (PROGRAMMING OF

THE DLD DELAY COUNTER) WITH THE

REFERENCE AND FEEDBACK CLOCKS

INSIDE THE LOCK WINDOW AT THE PFD.

THIS ENSURES THAT THE HOLDOVER

FUNCTION WAITS FOR THE PLL TO SETTLE

AND LOCK BEFORE THE HOLDOVER

FUNCTION CAN BE RETRIGGERED.

Figure 47. Flowchart of Automatic/Internal Holdover Mode

The following registers affect the automatic/internal holdover

function:



how many consecutive PFD cycles with edges inside the

lock detect window are required for the DLD indicator to

indicate lock. This impacts the time required before the LD

pin can begin to charge as well as the delay from the end of a

holdover event until the holdover function can be reengaged.



must be set to 0b to enable the DLD circuit. Automatic/

internal holdover does not operate correctly without the

DLD function enabled.



to 000100b to program the current source lock detect mode

if using the LD pin comparator. Load the LD pin with

a capacitor of an appropriate value.



enable; 0b = disable. When disabled, the holdover function

always senses the LD pin as high.



disabled, both external and automatic/ internal holdover

are disabled.

In the following example, automatic holdover is configured with



Automatic reference switchover, prefer REF1.



Digital lock detect: five PFD cycles, high range window.



Automatic holdover using the LD pin comparator.

The following registers are set (in addition to the normal PLL

registers):



range.



current source lock detect mode.



buffers.



use automatic/internal holdover mode.



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