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AD9520-1/PCBZ датащи(PDF) 25 Page - Analog Devices

номер детали AD9520-1/PCBZ
подробное описание детали  12 LVPECL/24 CMOS Output Clock Generator
PDF  80 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9520-1/PCBZ датащи(HTML) 25 Page - Analog Devices

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Data Sheet
AD9520-1
Rev. B | Page 25 of 80
–100
–160
–150
–140
–130
–120
–110
1k
100M
1M
10M
100k
10k
NOTES
1. THE LOOP FILTER USED TO GENERATE THIS PLOT IS SHOWN IN FIGURE 41.
FREQUENCY (Hz)
Figure 30. Phase Noise (Absolute) Clock Generation; Internal VCO at
2.458 GHz; PFD = 15.36 MHz; LBW = 40 kHz; LVPECL Output = 122.88 MHz
1k
100M
1M
10M
100k
10k
FREQUENCY (Hz)
–120
–160
–150
–140
–130
Figure 31. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
–80
–90
–100
–110
–120
–130
–140
–150
–160
1k
100M
1M
10M
100k
NOTES
1. THE LOOP FILTER USED TO GENERATE THIS PLOT IS SHOWN IN FIGURE 42.
10k
FREQUENCY (Hz)
INTEGRATED RMS JITTER (12kHz TO 20MHz): 582 fs
Figure 32. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 2.488 GHz;
PFD = 120 kHz; LBW = 1.84 kHz; LVPECL Output = 155.52 MHz
1000
100
10
1
0.1
0.01
0.1
1
10
100
1000
JITTER FREQUENCY (kHz)
OC-48 OBJECTIVE MASK
AD9520
NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
fOBJ
Figure 33. Telcordia GR-253 Jitter Tolerance Plot



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